Digital Logic: Understanding Bit Storage and Flip-Flops, Study notes of Electrical and Electronics Engineering

Download Digital Logic: Understanding Bit Storage and Flip-Flops and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! 1 ECE 274 - Digital Logic Chapter 7: Flip-Flops, Registers, and Counters Lecture 16 Basic Latch (7.1) SR Latch (7.2) D Latch (7.3) D Flip-flop (7.4) SKIP T and JK flip-flops (7.5 and 7.6) Latch vs. Flip-Flop (7.7) 2 ECE 274 - Digital Logic Combinational vs. Sequential Circuits push button (input), bell rings (output) Door Bell Garage Door push button (input), if door open (state), close door (output) push button (input), if door closed (state), open door (output) Combinational Circuit Design Output is a combination of input values No memory; there is no way to remember previous inputs or outputs Sequential circuits Output is a combination of current input values and circuit’s current state (previous input values) Remembers results of previous operations NEED A WAY TO STORE STATE! 3 ECE 274 - Digital Logic Example System Illustrating Need for Bit Storage Bit Storage Red lightCall button Cancel button Bit Storage Red lightCall button Cancel button 2. Call button released – light stays on Bit Storage Red lightCall button Cancel button 3. Cancel button pressed – light turns off 1. Call button pressed – light turns on QCall Cancel Doesn’t work. Q=1 when Call=1, but doesn’t stay 1 when Call returns to 0 Need some form of “feedback” in the circuit Flight attendant call button Press call: light turns on Stays on after button released Press cancel: light turns off Logic gate circuit to implement this? 4 ECE 274 - Digital Logic First Attempt at Bit Storage QS t 0 t 0 QS 0 1 0 1 0 1 0Q t S 0 t 1 QS 0 0 t 1 QS 1 1 t 1 QS 1 1 t 0 QS 1 We need some sort of feedback Does circuit on the right do what we want? No: Once Q becomes 1 (when S=1), Q stays 1 forever – no value of S can bring Q back to 0 5 0 t Q S=1 R=0 1 t Q S=0 R=0 1 0 ECE 274 - Digital Logic Bit Storage Using an SR Latch Q S (set) SR latch R (reset) 1 0 1 0 R S 1 0 t 1 0 Q 1 t Q R=0 S=0 0 0 1 1 X 0 R ecal. Recall… Does the circuit to the right, with cross-coupled NOR gates, do what we want? Yes! R=1 t Q S=0 0 1 0 0 1 1 0 1 01 0 6 ECE 274 - Digital Logic Example Using SR Latch for Bit Storage R S Q Red light Call button Cancel button Bit Storage Red lightCall button Cancel button SR latch can serve as bit storage in previous example of flight-attendant call button Call=1 : sets Q to 1 Q stays 1 even after Call=0 Cancel=1 : resets Q to 0 But, there’s a problem... 13 ECE 274 - Digital Logic Level-Sensitive D Latch R S D C D latch Q 1 0 D C S R Q 1 0 1 0 1 0 1 0 D Q’ QC D latch symbol SR latch requires careful design to ensure SR=11 never occurs D latch relieves designer of that burden Inserted inverter ensures R always opposite of S 14 ECE 274 - Digital Logic Problem With Level-Sensitive D-Latch D1 Q1 D2 Q2 D3 Q3 D4 C4C3C2C1 Q4Y Clk Clk_A Clk_B Clk rising edges D latch still has problem (as does SR latch) When C=1, through how many latches will a signal travel? Depends on for how long C=1 Clk_A -- signal may travel through multiple latches Clk_B -- signal may travel through fewer latches Hard to pick C that is just the right length Can we design bit storage that only stores a value on the rising edge of a clock signal? 15 ECE 274 - Digital Logic D Flip-Flop Note: Hundreds of different flip-flop designs exist D latch master D latch servant D Dm Ds Cs Qm Qs’ Qs Q Q’ Cm Clk D flip-flop Flip-flop Bit storage that stores on clock edge, not level One design is called master- servant Output of master latch is input to servant latch Master has inverted clock signal Servant has direct clock signal 16 ECE 274 - Digital Logic D Flip-Flop Clk D/Dm Qm/Ds Cm Cs Qs D latch master D latch servant D Dm Ds Cs Qm Qs’ Qs Q Q’ Cm Clk D flip-flop How does it work? Master loaded when C=0, Servant loaded when C=1 When C = 0 Master loaded with value from D Servant disabled When C = 1 Master disabled, holds value from D Servant loaded with output from Master (value that was at D just before C changed) 17 ECE 274 - Digital Logic Rising vs. Falling Edge Triggered Flip-Flop Q’D Q D Q’ Q Symbol for rising-edge triggered D flip-flop Symbol for falling-edge triggered D flip-flop Clk rising edges Clk falling edges The triangle means clock input, edge triggered We can design flip-flop to operate on either rising or falling edge of clock signal Depends on which flip-flop (master or servant) has inverted clock signal 18 ECE 274 - Digital Logic No More Unknown Propogation Two latches inside each flip-flop D1 Q1 D2 Q2 D3 Q3 D4 Q4Y Clk Clk_A Clk_B T w o l a t ches insde ach fli p -flop Solves problem of not knowing through how many latches a signal travels when C=1 In figure below, signal travels through exactly one flip-flop Same for Clk_A or Clk_B Why? Because on rising edge of Clk, all four flip-flops are loaded simultaneously -- then all four no longer pay attention to their input, until the next rising edge. Doesn’t matter how long Clk is 1. 19 ECE 274 - Digital Logic Latch vs. Flip-flop Behavior Clk D Q (D latch) Q (D flip-flop) 10 87 654 9 3 1 2 Latch is level-sensitive Stores Input D when C=1 Flip-flop is edge triggered Stores Input D when C changes from 0 to 1 Two types of flip-flops -- rising or falling edge triggered 20 ECE 274 - Digital Logic Flight-Attendant Call Button System Using D Flip-Flop Preserve value: if Q=0, make D=0; if Q=1, make D=1 Cancel -- make D=0 Call -- make D=1 Let’s give priority to Call, make D=1 D flip-flop will store bit Inputs are Call, Cancel, and present value of D flip-flop, Q Truth table shown below Flight attendant call- button system Red lightCall button Cancel button D Q’ QClk Call Cancel Q Red light Call button Cancel button We know how to convert truth table to circuit. Circuit output D is input to Flip-flop 21 ECE 274 - Digital Logic Rising vs. Falling Edge Triggered Flip-Flop Bubble indicates signal is active low, corresponding action happens when signal value = 0 Latches can also include other inputs Preset Preset = 1, no effect Preset = 0, sets output Q = 1 Clear Clear = 1, no effect Clear = 0, sets output Q = 0 D Q’ Q Clear Preset D Q’ Q Clear Preset 0 1 D Q’ Q Clear Preset 0 0