Flipflop, Bit Register and the Register Files | CPSC 5155G, Study notes of Computer Architecture and Organization

Download Flipflop, Bit Register and the Register Files | CPSC 5155G and more Study notes Computer Architecture and Organization in PDF only on Docsity! Chapter 6 Flip-Flops, Registers, and Register Files A 4+-Bit Register This uses four D flip-flops. *s DO our, cK ——— TM = —pD Q OUT, CLE | in Z na amr, ele ae | Se 5sttean~ oT Dea OULy Ce loci CLE “—_——_s LoaD [oH Cluck When the LOAD signal is asserted, the register 1s loaded. Slide | of 14 slides CPSC 5155 Revised February 1, 2006 Chapter 6 Flip-Flops, Registers, and Register Files More on the LOAD Signal. All control signals are generated by a control unit, which interprets the machine language representing the program. When looking at components in isolation, we usually do not consider the source of the control signal, but assume it is generated validly. The control signal must be generated in tume with the system clock. Proper ‘I do Short Losie 1 Togie 0 Logic 1 Load Lugied [_ _t [ Lugic L Clock Logie 0 Slide 2 of 14 slides CPSC 5155 Revised February 1, 2006 Chapter 6 Flip-Flops, Registers, and Register Files Register Functionality A register controller should select from three functions (not two). 1) Donothing — save the current contents 2) Copy the mput to the register and possibly change its contents 3) Copy the register contents to the output. Atse-savethe-comtents. This requires as least two control signals as 2° < 3 < 2°. The previous example used Select and Load. Select | Load Action 0 0 |Donothing 0 1 Do nothing 1 0 |Copy data from register 1 1 | Load data into register Slide 5 of 14 slides CPSC 5155 Revised February 1, 2006 Chapter 6 Flip-Flops, Registers, and Register Files Example of a Four General Purpose Register File | Legs Lins Yr) +> Raw» 7 ez — Clock} Oo12723 Aud Devuder Bus+Rea hy Ry Two-bit data buses and two-bit registers. Where is RO? Slide dof 14 slides CPSC 5155 Revised February 1, 2006 oO Chapter 6 Flip-Flops, Registers, and Register Files Loading the Registers Control signals are Bus + Reg, Reg > Bus, and the two-bit binary number R,Ro, used to select the register. A Decoder generates the load signal for each register. _|i 1] 012 3 2-to-4 Decoder Bus+Reg 7 R 1] 0 NOTE: The decoder is enabled by the Bus — Reg signal. If Bus > Reg = 0, no register 1s loaded. There is no signal to load register 0 as there is no register 0. Slide 7 of 14 slides CPSC 5155 Revised February 1, 2006 Chapter 6 Flip-Flops, Registers, and Register Files How to Load a JK: Correct Version This also applies to SR flip-flops. x Load. wae, > If Load = 0, then J=0andk=0 If Load = 1 then J= X and K = Not(X). Slide 10 of 14 slides CPSC 5155 Revised February 1, 2006 QL. Chapter 6 Flip-Flops, Registers, and Register Files How Not to Load a JK: Mistake One — | pat Load 4 J 0} « ro The Load signal is asserted only when the register 1s to be loaded. Works OK if Load = 1. If Load = 1, then J=X and K=Not(X). If Load = 0, then J=0OandK=1. This isthe “autoforget” memory. Slide 11 of 14 slides CPSC 5155 Revised February 1, 2006 Chapter 6 Flip-Flops, Registers, and Register Files How Not to Load a JK: Mistake Two x | y Qe Load K gt Again, this works when Load = 1. Loat =o If Load = |, then 5 J=X and K= Not(X). C If Load = 0, then neither J nor K is defined. a" What happens depends on how the flip-flop is built. L— RULE: Don’t use tn—states on inputs. J «eK net rweAl, Slide 12 of 14 slides CPSC 5155 Revised February 1, 2006