Formal Verification of Hardware/SoC: CTL Model Checking and Composing Modalities - Prof. S, Study notes of Electrical and Electronics Engineering

Download Formal Verification of Hardware/SoC: CTL Model Checking and Composing Modalities - Prof. S and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! ECE 598 SV Formal Hardware/SoC Verification CTL Model Checking EG p After the first iteration (shown above), τ 1 (true) = p ^ EX true = p All states are marked (tick sign), where p holds. After the second iteration, τ 2 (true) = p ^ EX p Marked states are such that p holds, and p holds in atleast one of the next states. After the third iteration, τ 3 (true) = p ^ EX (p ^ EX p) τ 4 (true) = τ 3 (true) So, this is the greatest fixed point. Note that at iteration i, we are left with the set of states such that there exists a path of length i where every state satisfies p. AG p Holds in the above example, if it had p in the 4 th state as well. τ 1 (true) = p ^ AX true τ 2 (true) = p ^ AX p = τ 1 (true) AF p p After the first iteration (shown above), τ 1 (false) = p ∨ AX false No states are marked. p After the second iteration (shown above), τ 2 (false) = p ∨ AX p EFEG p EG p is not satisfied (p doesn’t hold in first 2 states on the path). EFEG p is satisfied. EGEF p EF p is satisfied. EGEF p is also satisfied. However, EGEF p would fail without the lower p. This behavior is not captured by using just EF p. EGAF p AF p is satisfied. EGAF p is not satisfied. States immediately below the horizontal line do not satisfy AF p. AFAG p AG p doesn’t hold. It requires all states to be labeled with p. AFAG p is satisfied. All paths eventually end in a subtree where AG p holds.