Pulse-Width Modulated DC-DC Converters: Fundamentals & Steady-State Behavior - Prof. Georg, Study notes of Electrical and Electronics Engineering

Download Pulse-Width Modulated DC-DC Converters: Fundamentals & Steady-State Behavior - Prof. Georg and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! 1 LECTURE 8 Fundamental Models of Pulse-Width Modulated DC-DC Converters: f(D) I. Quasi-Static Approximation A. Linear Models/ Small Signals/ Quasistatic ∆V I C dt= Amp-Sec/Farad ∆I V L dt= Volt-Sec/Henry 1. Switched Capacitor Network Dynamics and in Steady-State 2. Switched Inductor Network Dynamics and in Steady-State a. General Issues of iL(t) b. Buck Circuit Topology c. Boost Circuit Topology d. Buck-Boost Circuit Topology B. EXAMPLE OF BOOST DESIGN 2 I. Quasi-static Approximation Quasi-static Basic Review: Signals in the quasistatic case DC V,I t Linear slope for small ∆v,∆i Exponential behavior Usually in simple RC and LR circuits there is an exponential change of signals from 0 → V(dc), I(dc) A useful approximation is: for τ = RC is that the exponential signal reaches a certain percent of final at various nτ. ln10 * τ → 9 0% at 2.3τ 2ln10 * τ → 9 9 % at 4.6τ 3ln10 * τ → 9 9 .9 % at (3 * 2.3 = 6.9 τ) τ = RC sec for V τ = L/R sec for I But for times much less than τ, linear behavior occurs allowing great simplification. In switching rather than exponential circuits fsw and Tsw are chosen such that they are much smaller than the RC and L/R time constants. A. Small signal linear model In short, since we usually have in dc-dc converters ac changes that are small, and switching times much faster than circuit time constants we can use simple linear relationships rather than differential equations. 5 2. Switched inductor in steady state We apply a square wave across VL and see iL vary as a triangle wave. a. General iL vs. time over Ts Ipeak Imin IL(DC) DTs D'Ts I t Ts su sd IL(Ts) IL(0) ramp down ramp up VL(D) = su L VL(D') = sd L Assume vL during DTs is positive and that vL during D’Ts is negative. In the most general case, |vL(DTs)| ≠ |vL(D’Ts)| due to different switched topology of circuit during DTs and D’Ts. ∆i L V dt L= ≡∫1 amperes We repeat that VL(DTs) ≠ VL(DTs) due to different switched voltages. We assumed that for steady state to occur in an inductor over one switching period iL(Ts) ≡ iL(0) or suDTs = sdD’Ts. Otherwise, iL drifts upwards or downwards until i > i(critical) causing inductor core saturation. Note: starting at iL(0) going to IL(DC) over a time DTs, i DT i s DTL s L u s( ) ( )= +0 6 D I DC i s T i s T L L u s u s = − =( ) ∆ The proper D value is self-set for steady state to occur, likewise starting at IL(DC) @ DTs going back to iL(0) at Ts takes D’Ts to accomplish. i T i i DT s D TL s L L s d s( ) ( ) ( ) '= = −0 0 = −s DT s D Tu s d s' ← Volt-sec balance in steady state. s s D D d u = ' That is for steady state to occur the smaller the off fraction D’ the larger the discharge slope sd must be and the bigger the on time D the smaller su must be. b. Buck Circuit Topology In the Buck the inductor position in the circuit topology of the dc-dc converter varies but it always has the switch attached. To avoid KVL violations we need to have an inductor to buffer the Vout and Vin which are temporarily connected by the switch network. Here Vo = DVin and Vo cannot exceed Vin. The right side of L is fixed at Vo which for regulated of feedback supplies is often dead constant. The left side of L is switched from Vg to ground. Vg sometimes varies for raw or unfiltered DC but is usually considered constant as well. Over the period Ts the switch goes up for a time DTs and down for a time D’Ts. 7 Vg Vout L IL For switch up: s V V L A su g o= − ( / ) For switch down: ( )s V L A sd o= − / a very fixed slope Buck example: For Vg = 20 and Vo = 15 we find D = 0.75 for Buck topology. The vL and iL output waveforms for the buck are shown below: 0 V ol ta ge Vin <vout> time 2TT0 vout(t) IL 150100500 IL(t) Note: 1. Vo = DVin 2. Iin = DIout 3. Po = Pin = DVinIout 4. Vout(rms) = D Vin 5. What is Iout(rms)? A simple dc motor control is shown below. Recall that Vg = kφw(motor rotation). By setting VT(DC) via D we can determine motor speed. 10 i = C dv/dt(off time of the diode) 0.42 = C 2.4/2.1 µs C > 83.3 µF for ∆Vo < 0.01 Finally prove to your self that a + 50 ns time jitter on the transistor switch time causes Vout to vary from 117 to 123 V or + 2.5%. d. Buck-Boost Circuit Topology Bottom of L is fixed at ground while the top side switches from Vg to Vo. For the case of feedback in the circuit, Vg could be crude rectified DC and Vo regulated DC. Here Vo/Vin = D/D’ and the output is opposite polarity to the input moreover we overcome the Vout < Vin limitation of the buck and the Vout > Vin limitation of the boost. No KVL violations occur as each voltage supply only sees L which appears as a current source. For analysis below we assume both do not vary over Ts. VoutLVg Switch at Vg: s V L A su g= ( / ) Switch at Vout: s V L A sd out= ( / ) sd very fixed for feedback case ⇒ V V D D out g = − ' 11 Now, by inspection, a buck-boost has the simple slopes switched since no potential difference occurs in VL: IDC t D'TsDTs iL su sd Upslope: s V L A su g= ( / ) Downslope: s V Ld out= (A / s) •Buck-boost is easy because there are no complex differences to calculate for vL since one side of L is always grounded. vL is either Vg or Vo. •In contrast for buck and boost circuit topologies one finds for the voltage across L: VL ∼ (Vg - Vo) and both relative magnitudes affect ∆i slopes. B.EXAMPLES OF BOOST DESIGN Below we will go through the flow of a boost design- a flyback converter, which is a subset of the boost topology. The object is to see how much design you are already to do and how much you are not ready to do. Also it puts into better perspective the filter design as part of the whole design process. The input voltage of 18- 36 volts is representative of the factor of 2 range of input voltage variation we must deal with. The 12 multiple outputs at set current levels at each load is also typical. Note in the figure below the single input and multiple output filters as well as the switch transistor Q2 and its control circuits. Next we do a black-box overview that allows us to find required power, current and wire sizes. 15 It is this filter capacitor to which we turn our attention. The less ripple desired on the input DC the larger the capacitor but this causes large surge currents on start-up. As a guide we state that ripple voltages of 0.5 to 2 Volts are tolerable. Capacitors with low ESR are assumed here so only the C contributes to ripple voltages. One can show that: Cin =2x P(input average)/ fswx (Vripple)2 We will assume V ripple is 1 Volt. Finally, in the circuit diagram of page 12 the controller chip provides: • The settings to make our desired first choice for fsw to be 40 KhZ • Current mode control circuits we will cover later • Driver circuits to turn on and off the switch transistor The switch-mode controller In attempting to select a controller IC one should make a list of the important features desired for the design. Also make a “nice but nonessen- tial” list. Essential “Nice—but” Low parts count Undervoltage lockout Current-mode control Low Jeense threshold MOSFET driver output (totem-pole) 50 percent duty cycle limiting Single output driver Low cost After reviewing the list of popular controller ICs, the UC3845P appears to satisfy all the above requirements. “ Referring to the data sheet in the Motorola “Linear and Interface Integrated Circuits” data book, the basic schematic implementation is given in the application figures. The designer need only determine the values for the timing resistor and capacitor, and the current-sense resistor. All of the other components are involved with the V.. supply and the feedback compensation, which will be designed later. Looking at the “Timing Resistor vs. Oscillator Frequency” graph and wishing to Operate the supply at a nominal 40 kHz, one determines values of Cr = Cy = 2000 pF. Ry = Ry = 10K. This value will no doubt need to be adjusted during the breadboard stage.