VHDL Language Overview III: Understanding Entities, Architectures, and Packages, Slides of Verilog and VHDL

Download VHDL Language Overview III: Understanding Entities, Architectures, and Packages and more Slides Verilog and VHDL in PDF only on Docsity! Language Overview III The finish of a grand tour of the language. Docsity.com Elements Covered in III • Reminder from I and II: Language overview lectures do not cover all aspects of the language. But they do cover a large portion of it. – Concurrent Statements – Sequential Statements • Now – ENTITIES, ARCHITECTURES, PACKAGES, PROCEDURES AND FUNCTIONS, OVERLOADING, LIBRARIES and the USE clause. Docsity.com The ENTITY – formal_generic_clause::= generic (generic_list); – formal_port_clause::= port (port_list); – entity_declarative_part::= {entity_declarative_item} – entity_declarative_item::= – subprogram_declaration – | subprogram_body – | type_declaration – | subtype_declaration – | constant_declaration – | signal_declaration – | file_declaration – | alias_declaration – | attribute_declaration – | attribute_specification – | disconnect_specification – | use_clause Items declared in the ENTITY have scope over all architectures of the entity Docsity.com The ENTITY – entity_statement_part::= entity_statement – entity_statement::= – concurrent_assertion_statement – | passive_concurrent_procedure_call – | passive_process_statement • Passive means that the process or procedure call contains no signal assignment statements, nor calls to any other procedure which contains a signal assignment statement. • Thus these passive procedure calls and processes can do monitoring only. They can use assertion statements to report status of the signals they are monitoring. Docsity.com The ENTITY • EXAMPLE – entity LATCH is – port (DIN: in WORD; DOUT: out WORD; – LOAD, CLK : in BIT); – constant SETUP : TIME := 12 ns; – constant PulseWidth : TIME := 50 ns; – use WORK.TimingMonitors.all; – begin – CheckTiming (SETUP,DIN,LOAD,CLK); – end LATCH; Docsity.com The Architecture – architecture_declarative_item::= – subprogram_declaration – | subprogram_body – | type_declaration – | subtype_declaration – | constant_declaration – | signal_declaration – | file_declaration – | alias_declaration – | component_declaration – | attribute_declaration – | attribute_specification – | configuration_specification – | disconnect_specification – | use_clause Docsity.com Packages • Packages provide a convenient way to declare commonly used declarations, functions, and procedures and make them available to many entities, architectures, and other packages. • Consists of two parts – The Package Declaration – The Package Body Docsity.com Package Declaration – package identifier is – package_declarative_part – end [identifier]; – package_declarative_part::={package_declarative_item} – package_declarative_item::= – subprogram_declaration – | type_declaration – | subtype_declaration – | constant_declaration – | signal_declaration – | file_declaration – | alias_declaration – | component_declaration – | attribute_declaration – | attribute_specification – | disconnect_specification – | use_clause Docsity.com Example – package body TriState is – function BitVal (value:TRI) return BIT is – constant bits : BIT_VECTOR := (“0100”); – begin – return bits(TRI’POS(value)); – end; – function TriVal (value:BIT) return Tri is – begin – return Tri’Val(BIT’POS(value)); – end; Docsity.com Notes on Packages • Note: Only what is declared in the package declaration is visible outside the package!!! • Items declared inside the package body are only visible inside the package body. Docsity.com Functions and Procedures • Sequential statements are used within Functions and Procedures • Declaration – procedure designator [(formal_parameter_list)]; – function designator [(formal_parameter_list)] – return type_mark; Docsity.com Other item of significance - OVERLOADING • Overloading – You can overload any function or procedure in VHDL. • EXAMPLE: – procedure WRITE (F: inout TEXT; value:Integer); – procedure WRITE (F: inout TEXT; value : String); – These are two declarations for an overloaded procedure WRITE – (if no mode is given on the arguments to a procedure or function the mode IN is presumed) – USAGE DETERMINES WHICH VERSION OF THE PROCEDURE WILL BE USED – USAGE • write (MY_FILE, VAR); • WRITE(sys_output, 12); WRITE(sys_error, “Actual output doesn’t match”); Docsity.com Overloaded Functions – type MVL is (‘0’,’1’,’Z’,’X’); – function “and” (L,R : MVL) return MVL; – function “or” (L,R : MVL) return MVL; – USAGE: • signal Q,R,S : MVL • Q <= ‘X’ or ‘1’; • R <= S and Q; Docsity.com Libraries and Use • Libraries provide a place to organize and store the design units – entities – architectures – package declarations – package bodies – that we have written and analyzed. • Then to use those design units we need to make them visible with the current design unit so it can see, and thus use, them. Docsity.com Library Clause and Packages • The library clause only makes the entities visible. It does not make any declarations within the package visible. • Need to use a USE clause to make package declarations visible. • USE clause: – use library_name.package_name.items • where items may be specific items or the reserved word all Docsity.com Example of USE – library ls7400; – use ls7400.gates.all; – entity new_thing is ….. • where gates is a package with library ls7400. • The all makes all declarations in package gates visible. • ALL DESIGN UNITS ARE CONSIDERED TO HAVE – library WORK, STD; – use STD.STANDARD.ALL; Docsity.com A final note • If you write a package and analyze it into library WORK, to use the declarations there you need to have a use clause. – use WORK.TriState.TRI,WORK.TriState.BitVal; – Or could have use.WORK.TriState.ALL; – This makes the type TRI and the function BitVal visible to the current design unit in addition to STD.STANDARD.ALL – EXAMPLE SLIDE for type compatability Docsity.com