VHDL Overview: Understanding Hardware Description Language and Its Usage, Slides of Digital Systems Design

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L9 – VHDL Overview Docsity.com VHDL Overview • Rules for State Assignment • Application of rule • Gate Implementation • Ref: text Unit 15.8 Docsity.com Common to all systems • Have source HDL file • Structure of generated files is common • Library files are • for design units Source Files VHDL Library Files Analysis (Compile) Simulation Synthesis Docsity.com A First Example • Desire to do a VHDL description of a full adder. • A device consists of – An Interface – An operational part • Interface – The INPUTS AND OUTPUTS • Operational Part – The FUNCTIONAL BEHAVIOR Docsity.com VHDL Entity Design Unit • Format – ENTITY unit_name IS – [port_clause] – END unit_name; • For a full adder would have: – ENTITY full_adder IS – PORT(a,b,cin : IN bit; – sum : OUT bit; – cout : OUT bit); – END full_adder; • The PORT portion is termed a Port Clause – When specified in the port clause these signals have scope over all architectures of this entity Docsity.com Basic Types • Built in – part of the standard and the language proper. • TYPE BIT – your typical binary type with values of ‘0’ and ‘1’. – Declaration that established this type • TYPE BIT is (‘0’, ‘1’); – Use of SIGNALS of TYPE bit – a <= ‘0’; – b <= x AND y OR z; • Note that the value is either ‘0’ or ‘1’ Docsity.com Architectural Design Unit • Specifies the operational part – ARCHITECTURE identifier OF entity_id IS – [declarations] – BEGIN – [architecture_statement_part] – END [identifier]; – [architecture_statement_part] – Any concurrent statement of the language Docsity.com Example of Architecture • For a full adder – ARCHITECTURE one OF fulladder IS – BEGIN – sum <= a XOR b XOR cin; – cout <= (a AND b) OR (a AND cin) OR (b – AND cin); – END one; • This style of description is referred to as a dataflow description. It is excellent for the combinational logic leaf units of a design. Docsity.com The first dataflow Architecture • ARCHITECTURE one OF mb_adder IS • SIGNAL c : BIT_VECTOR (4 downto 0); • BEGIN • c(0) <= cin; • sum(0) <= a(0) XOR b(0) XOR c(0); • sum(1) <= a(1) XOR b(1) XOR c(1); • sum(2) <= a(2) XOR b(2) XOR c(2); • sum(3) <= a(3) XOR b(3) XOR c(3); • c(1) <= (a(0) AND b(0)) OR (a(0) AND c(0)) OR • (b(0) AND c(0)); • c(2) <= (a(1) AND b(1)) OR (a(1) AND c(1)) OR • (b(1) AND c(1)); • c(3) <= (a(2) AND b(2)) OR (a(2) AND c(2)) OR • (b(2) AND c(2)); • c(4) <= (a(3) AND b(3)) OR (a(3) AND c(3)) OR • (b(3) AND c(3)); • Cout <= c(4); • END one; Docsity.com Dataflow Architectures • Dataflow architectures should be limited to leaf units. • The level of complexity should be limited. • The 4 bit adder is not overbearing but much more than this should be avoided. • Probably want to limit dataflow descriptions to 30 or so lines. • Dataflow architectures synthesize extremely well across most synthesis tools (Altera, Xilinx, Synopsis, Mentor Graphics) Docsity.com The Second Dataflow Architecture – ARCHITECTURE two OF mb_adder IS – SIGNAL c : BIT_VECTOR (4 downto 0); – BEGIN – c(0) <= cin; – sum <= a XOR b XOR c(3 downto 0); – c(4 downto 1) <= (a(3 downto 0) AND b(3 downto 0)) – OR (a(3 downto 0) AND c(3 downto 0)) OR – (b(3 downto 0) AND c(3 downto 0)); – Cout <= c(4); – END two; • Note the power of this HDL specification • The Carry ripples through repeated evaluations of the equation as whenever a signal on the right-hand-side changes, the equation is re-evaluated and a new value scheduled for assignment to the signal. • Also synthesizes well. Docsity.com VHDL Structural Example • Again consider the full adder • Before doing a structural description must have the components that are going to be wired together. These must first be written and compiled into the library. • Only the ENTITIES are given. Each would have an architecture. – ENTITY and2 IS – PORT (A,B : IN BIT; Z : OUT BIT); – END and2; • – ENTITY xor2 IS – PORT (A,B : IN BIT; Z : OUT BIT); – END xor; • – ENTITY or3 IS – PORT (A,B,C : IN BIT; Z : OUT BIT); – END or3; Docsity.com The AND and OR gates • AND 2 – ENTITY and2 IS – PORT (A,B : IN BIT; Z : OUT BIT); – END and2; – ARCHITECTURE one OF and2 IS – BEGIN – Z <= A and B AFTER 2 ns; – END one; • OR2 – ENTITY or2 IS – PORT (A,B : IN BIT; Z ; OUT BIT); – END or2; – ARCHITECTURE one OF or2 IS – BEGIN – Z <= A or B AFTER 2 ns; – END one; Docsity.com Structural Example for a full adder • The first part – ARCHITECTURE structural OF full_adder IS – -- Must declare the components that are to be used – COMPONENT and2 – PORT (A,B : IN BIT; Z : OUT BIT); – END COMPONENT ; – COMPONENT xor2 – PORT (A,B : IN BIT; Z : OUT BIT); – END COMPONENT ; – COMPONENT or3 – PORT (A,B,C : IN BIT; Z : OUT BIT); – END COMPONENT ; – -- State which library to find them in and which architecture to use. – FOR ALL : and2 USE ENTITY WORK.and2(behavioral); – FOR ALL : xor2 USE ENTITY WORK.xor2(behavioral); – FOR ALL : or3 USE ENTITY WORK.or3(behavioral); – -- Declare local signals required. – SIGNAL addt. ct1, ct2, ct3 : BIT; Docsity.com The multibit Architecture • ARCHITECTURE structural OF mb_adder IS • -- Must declare the components that are to be used • COMPONENT full_adder • PORT( a,b,cin : IN BIT; • sum : OUT BIT; • cout : OUT BIT); • END COMPONENT; • FOR ALL full_adder USE ENTITY work.full_adder(structural); • SIGNAL ic1,ic2,ic3 BIT; • BEGIN • U0: full_adder(a(0),b(0),cin,ic1,sum(0)): • U1: full_adder(a(1),b(1),ic1,ic2,sum(1)): • U2: full_adder(a(2),b(2),ic2,ic3,sum(2)): • U3: full_adder(a(3),b(3),ic3,cout,sum(3)): • END structural; Docsity.com Lecture summary • A note on VHDL styles: – The dataflow style synthesizes well. – The structural style synthesizes well. • Have seen several initial examples of VHDL code. • Will now focus on that part of the language for small dataflow and state machine designs. • Pick a problem Docsity.com