Interrupt Handling and CPU State in Computer Systems: A Study Guide for 15-410 Students, Slides of Software Engineering

Download Interrupt Handling and CPU State in Computer Systems: A Study Guide for 15-410 Students and more Slides Software Engineering in PDF only on Docsity! 15-410, F’111 Hardware Overview Sep. 7, 2011 Dave Eckhardt Garth Gibson L04_Hardware 15-410 “Computers make very fast, very accurate mistakes.” --Brandon Long 15-410, F’112 Synchronization Partner signups  11 group signups so far – thanks!  Please sign up as soon as you decide!  This helps other students  Both partners please sign up!  This helps course staff detect “love triangles” 15-410, F’115 Synchronization Simics on Windows?  Simics simulator itself is available for Windows  15-410 build/debug infrastructure is not  Can be hacked up, issues may arise » Version skew, partner, ... Options  Dual-boot Linux/Windows, run Linux in VMware  Usability via X depends on network latency  May be too slow – though we are experimenting  Port to cygwin (may be non-trivial)  There are some cluster machines...  WeH 5205/5207, GHC 3000, GHC 5201/5205 15-410, F’116 Outline Computer hardware CPU State Fairy tales about system calls CPU context switch (intro) Interrupt handlers Race conditions Interrupt masking Sample hardware device – countdown timer 15-410, F’117 Inside The Box - Historical/Logical CPU Memory Graphics Ethernet IDE Floppy USB 15-410, F’1110 CPU State User registers (on Planet IA32)  General purpose - %eax, %ebx, %ecx, %edx  Stack Pointer - %esp  Frame Pointer - %ebp  Mysterious String Registers - %esi, %edi 15-410, F’1111 CPU State Non-user registers, a.k.a.... Processor status register(s)  Currently running: user code / kernel code?  Interrupts on / off  Virtual memory on / off  Memory model  small, medium, large, purple, dinosaur 15-410, F’1112 CPU State Floating point number registers  Logically part of “User registers”  Sometimes another “special” set of registers  Some machines don't have floating point  Some processes don't use floating point 15-410, F’1115 User Mode Operating System Process 1 Process 2 CPU 15-410, F’1116 Entering Kernel Mode Operating System Process 1 Process 2 CPU save 15-410, F’1117 Entering Kernel Mode Operating System Process 1 Process 2 CPU Ethernet SATA Floppy USB 15-410, F’1120 Returning to User Mode Operating System Process 1 Process 2 CPU restore 15-410, F’1121 The Story of getpid() What's the getpid() system call?  C function you call to get your process ID  “Single instruction” (INT) which modifies %eax  Privileged code which can access OS internal state 15-410, F’1122 A Story About read() User process is computing count = read(7, buf, sizeof (buf)); User process “goes to sleep” Operating system issues disk read Time passes Operating system copies data to user buffer User process “wakes up” 15-410, F’1125 Interrupt Vector Table How should CPU handle this particular interrupt?  Disk interrupt ⇒ invoke disk driver  Mouse interrupt ⇒ invoke mouse driver Need to know  Where to dump registers  Often: property of current process, not of interrupt  New register values to load into CPU  Key: new program counter, new status register » These define the new execution environment 15-410, F’1126 Interrupt Dispatch Table lookup  Interrupt controller says: this is interrupt source #3  CPU fetches table entry #3  Table base-pointer programmed in OS startup  Table-entry size defined by hardware Save old processor state Modify CPU state according to table entry Start running interrupt handler 15-410, F’1127 Interrupt Return “Return from interrupt” operation  Load saved processor state back into registers  Restoring program counter reactivates “old” code  Hardware instruction typically restores some state  Kernel code must restore the remainder 15-410, F’1130 Race Conditions Two concurrent activities  Computer program, disk drive Various execution sequences produce various “answers”  Disk interrupt before or after function call? Execution sequence is not controlled  So either outcome is possible “randomly” System produces random “answers”  One answer or another “wins the race” 15-410, F’1131 Race Conditions – Disk Device Driver “Top half” wants to launch disk-I/O requests  If disk is idle, send it the request  If disk is busy, queue request for later Interrupt handler action depends on queue status  Work in queue ⇒ transmit next request to disk  Queue empty ⇒ let disk go idle Various execution orders possible  Disk interrupt before or after “disk is idle” test? System produces random “answers”  “Work in queue ⇒ transmit next request” (good)  “Work in queue ⇒ let disk go idle” (what??) 15-410, F’1132 Race Conditions – Driver Skeleton dev_start(request) { if (device_idle) { device_idle = 0; send_device(request); } else { enqueue(request); } } dev_intr() { ...finish up previous request... if (new_request = head()) { send_device(new_request); } else device_idle = 1; } 15-410, F’1135 What Went Wrong? “Top half” ran its algorithm  Examine state  Commit to action Interrupt handler ran its algorithm  Examine state  Commit to action Various outcomes possible  Depends on exactly when interrupt handler runs System produces random “answers”  Study & avoid this in your P1! 15-410, F’1136 Interrupt Masking Two approaches  Temporarily suspend/mask/defer device interrupt while checking and enqueueing  Will cover further before Project 1  Or use a lock-free data structure  [left as an exercise for the reader] Considerations  Avoid blocking all interrupts  [not a big issue for 15-410]  Avoid blocking too long  Part of Project 1, Project 3 grading criteria 15-410, F’1137 Timer – Behavior Simple behavior  Count something  CPU cycles, bus cycles, microseconds  When you hit a limit, signal an interrupt  Reload counter to initial value  Done “in background” / “in hardware”  (Doesn't wait for software to do reload) Summary  No “requests”, no “results”  Steady stream of evenly-distributed interrupts