High Speed Pipelines Implementation - Advanced VLSI Design and Applications | ECEN 6263, Study notes of Electrical and Electronics Engineering

Download High Speed Pipelines Implementation - Advanced VLSI Design and Applications | ECEN 6263 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g n High Speed Pipeline Implementation (Cont.) Clocking Schemes for High Speed Domino Logic Fig. 7.43a, p. 427: Traditional domino clocking. While the clock is high, the first half of the domino gates evaluate. When the clock goes from high to low, the latch preserves the outputs from the first half which drives the second half while they evaluate. When the clock goes from low to high, the second latch preserves outputs and the process repeats. Since half of the domino gates evaluate while the other half precharges, no time is wasted by the precharge cycle. The latches must be between the domino gates clocked on different phases to hide the pre- charge signal from the following domino gates. The evaluation delay of a domino gate cannot straddle the clock phase boundary which eliminates the possibility of borrowing. Fig. 7.43b, p. 427: Clock skew must be accounted for each half cycle which doubles the time lost to clock skew margin. Fig. 7.44, p. 429: Latches can be eliminated provided that the clock signals overlap. This is the opposite of dynamic latches which require non-overlapping clocks. Fig. 7.45, p. 429: If keepers are used, a full keeper is required on the first domino gate in each clock phase. Fig. 7.46, p. 430: Skew tolerant domino. Skew is tolerable as long as it is less than the overlap. Limited borrowing is also possible during the overlap period. Fig. 7.47, p. 431: Local generation of overlapping clock phases from a single global clock. Since local clocks do not travel far, it is easy to keep small skew between the phases. Clock choppers delay the falling edge of clk and clkb to produce overlapping φ1 and φ2. Fig. 7.48, p. 431: OTB domino uses clk or clkb on the first domino gates in each phase to prevent incorrect operation from short contamination delays. Fig. 7.49, p. 432: Four phase domino. Contamination delays are not a problem since all 4 of the clock phases are never on at the same time. Since each phase overlaps the adjacent phase by T/4, skew and borrowing can be larger. Fig. 7.50, p. 432: Local clock generators for four phase overlapping clocks. Fig. 7.51, p. 434: N-phase domino. Delay chains produce clock phases for each domino gate. In (a), each global clock edge starts an evaluation of half of the domino gates which works even if the global clock is slow. In (b), the rising edge of the global clock triggers evaluation of all of the domino gates which requires a flip-flop to make sure that the last phase (φ6) overlaps the first phase (φ1) for slow global clocks.High Speed Pipeline Implementation (Cont.) November 24, 2006 page 1 of 5 E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g n Timing for Unfooted Domino Gates. Fig. 6.24, p. 333: Recall that the series precharge nFET can be eliminated to make “unfooted” domino gates. The series nFET makes sure that there is no path to ground dur- ing precharge. If the inputs can be guaranteed to be low during precharge, there is no need for the series nFET and a faster gate results. Fig. 6.28, p. 335: The outputs of the static gates (X and Z) are driven low during pre- charge and can be used as inputs to unfooted domino gates provided that the precharge of the unfooted gate is delayed until its inputs settle low. D yn am ic St at ic D yn am ic St at ic clk1 clk2 X Y Z clk1 clk2 W W X Y undelayed precharge normal precharge attempted pre- charge before X goes low delayed precharge normal precharge clk1 clk2 W X Yabnormal precharge normal precharge wait to pre- charge until X goes low Observe that a path to ground exists in the unfooted gate until X goes low. Excessive power consumption in the unfooted gate during precharge can be avoided by delaying the falling edge of clk2. Observe that the precharge of the unfooted domino is delayed in both High Speed Pipeline Implementation (Cont.) November 24, 2006 page 2 of 5