Bias Generator Design for High Temperature: Understanding Transistor Biasing and Equations, Study notes of Electrical and Electronics Engineering

Download Bias Generator Design for High Temperature: Understanding Transistor Biasing and Equations and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! 1 HIGH TEMPERATURE BIAS GENERATOR DESIGN Presented by : Chris Hutchens Oklahoma State University 2 Outline • Transistor • The Bias Generator Equation • VB1 and VB4 • VB3 and VB4 • Stacking Low VT and High VT devices • Stacking “zero” VT and Low VT devices • Start-up Circuit 5 SOI Square Law Point 1 a--- Square Law CAN TRANSITION TO MODERATE INVERSION Square Law ---M's ΔV > 250 to 300mV I1 = I2 = I 1 2 1 1 1 Veff1KPL @Wf I Δ⎟ ⎠ ⎞ ⎜ ⎝ ⎛= in Square Law 2 2 2 2 Veff2KPL @Wf I Δ⎟ ⎠ ⎞ ⎜ ⎝ ⎛= in Square Law 21 2 21 2 3 211 R 2 VVand ff I Δ=Δ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ −= β 4 9 f f 2 1 = is a nice ratio. I is proportional to μ Cox.! [ ] [ ] 122222 22 VVR VgmRVVIR Δ−Δ=⋅Δ=⋅ΔΔ= β ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ −= 1 2 2 12 S S gm R where gm = βΔV2 gm is set by selecting R and device geometry. 6 Squqre Law Bias Equation Point 1b --- Current Setting or Long Channel Bias DESIRED to Stabilize gm. Constant “Self Gain” 12 2 12 2 VVRVgmVVIR Δ−Δ=Δ⋅=Δ−Δ= ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ −=⎟ ⎠ ⎞⎜ ⎝ ⎛ Δ Δ−= 1 2 2 1 2 1 212 S S RV V R gm ---- Low TempCo R i.e. pos. tempCo combined with a neg. tempCo VB1 = VDD - |VTPL|- Veff VB4 = VSS + VTNL+ Veff • Improved Matching • Reduced 1/f noise • Improved PSRR • Higher gain M1 M2 VB1 VB4 7 Square Law Bias Equation Point 1c --- Constant “Veff or V swing” Long Channel Bias DESIRED to Stabilize Veff. 12 2 12 2 VVRVgmVVIR Δ−Δ=Δ⋅=Δ−Δ= ( )DDR VKPSS Sgm Δ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ −= 1 2 2 12 ---- MOS Resistor Veff = √m (SR/S)VDD - VT) DDR R VKPS gmS Δ ⋅ = 4 2 3 ( )effVKPSgm Δ= 22 VB1 = VDD - |VTPL|- Veff VB4 = VSS + VTNL+ Veff 10 Peregrine 0.5um SOS VB3 and VB2 Point 2a --- Cascode or Signal Transistors Bias VB3 = VB4 + VGS3 - VGS4 VB3 = VB4 + VTNs + 2Veff –[ VTNs +Veff/2 ] = VSS + VTNL+ Veff + VTNs + 2Veff –[ VTNs|+Veff/2 ] = VSS + VTNL+ 3/2 Veff And VB4 = VDD- |VTNL| + Veff VDSSAT + SM where SM is 25 to 200 mV MUST REQUIREMENT!! Optional M3 M4 11 Peregrine 0.5um SOS VB3 and VB2 Point 3 --- Cascode or Signal Transistors VDSSAT VB3 ≈ VSS + VTNL+ 2 Veff And VB4 = VSS- VTNL + 2 Veff VDSSAT + 100mV to 250mV MUST REQUIREMENT!! Selecting W = 2 verse 1 fingers provides a 83% decrease in Veff Selecting W = 48 verse 32 fingers provides a 20% decrease in Veff. Now for a Veff of 250mV of the safety margin on the current source becomes 103% or approximately 250mV. M3 M4 12 m=9 m=4 m=1 Peregrine 0.5um SOS Constant Gain Bias Point 4a --- Gain CONTANT with Temp /ggm A Odiff= Do I g effλ= ( )effdiffdiff VKPSgm Δ= ( )DDR VKPSS SVI Δ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ −Δ= 9 4 4 1 Proportional to mobility 40% decrease Temp 30 TO 200 0C ( ) 1 S A 9 4 4 diff λ α DDR eff VKPSS SV VKP Δ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ −Δ Δ⋅⋅ 15 Peregrine 0.5um SOS Constant gm bias Point 5b --- Gm and BW CONSTANT with Temp effeff diff V S S R V V Igm Δ ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ −Δ ⋅= Δ ⋅= 9 44 1 22 ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ −⋅ 9 412 S S R gmdiff α Bandwidth α gm 16 Peregrine 0.5um SOS Startup Circuit Point 6a --- Startup Ckt Required Bias Loop gain < 1 Required Very Small Possibility but still possib Many Versions 2 Possible Solutions 8 2@Wp/ 17 Peregrine 0.5um SOS Startup Circuit Point 6b --- Startup Loop Gain > 1 16/ >⋅≈⋅⋅= RgmRgmAA fol R > 6/gm = 3 ΔV/I Select R > 10 ΔV/I for VDS feedback > VTL+ VTsp+ VTL This ensures that the follower will shut off! R I + VTL > VDD. R >4 [ VDD - VTL ]/I Check for Strong Pull down! R m=9 m=4 m=1 20 SOI Moderate Inversion Point 7--- Subthreshold and Moderate Inv. Moderate Inversion ---M1 in subthreshold and M2 ΔV = 0V I1 = I2 = I IRe−⎟ ⎠ ⎞ ⎜ ⎝ ⎛= s 1 1 IL W I in Subthreshold ⎥⎦ ⎤ ⎢⎣ ⎡ +⎟ ⎠ ⎞ ⎜ ⎝ ⎛=⎥⎦ ⎤ ⎢⎣ ⎡ +⎟ ⎠ ⎞ ⎜ ⎝ ⎛= Δ TT nUnU V ee 0 2 s 2 2 s 2 2 1LNIL W 1LNI L W I at VGS = VT ( ) ( ) [ ]2LNIf If 2s2s1 =− IRe [ ] [ ] 42LN2 LNf f 422 2 1 >== IReeIR I 4 R > Vs is proportional to the UT2. Caution ( )2 LNIsIV 2 S ⋅== RR Is = 2•β(nUT)2 21 SOI Weak Inversion & BJTs RB M1 M2 RB Q1 Q2 S S/m AE 8 AE Point 7--- Subthreshold and BJTs. Moderate Inversion ---M1 in subthreshold and M2 ΔV = 0V I1 = I2 = I; VBE1 = VBE2 + IRB TBE nUVe /s1 1 I I = in BJTs; or ⎥⎦ ⎤ ⎢⎣ ⎡⋅⋅= Is ILNUnV TBE ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ ⋅⋅−⎥ ⎦ ⎤ ⎢ ⎣ ⎡ ⋅⋅= 21 Is ILNUn Is ILNUnIR TTB [ ] 28 1 2 ⋅ ⋅ =⋅ ⋅ =⎥ ⎦ ⎤ ⎢ ⎣ ⎡ ⋅ ⋅ = B T B T B T R Un LN R Un AE AE LN R Un I IPTAT – Current (I) Proportional To Absolute Temperature 22 Weak Inversion & BJTs IPTAT – Current (I) Proportional To Absolute Temperature Improved 25 SOI PSRR - plus Point 10--- Use of Long channel All regions • Decreased 1/f and thermal noise • Improved matching • Increased VA – o PSRR improved o ro and gain • Choice of cascode type depends on application circuit and best VA. I is proportional to μ Cox.! [ ] [ ] 22222 22 VR VgmRVVIR Δ⋅=⋅Δ=⋅ΔΔ= αβ 2 2 gm R ⋅= α gm is set by R Long Channel Long Channel Cascode Distribution I 4xWL/LL {mx4xWL}/LL I R = Veff2 /2 R =Veff/ m) R ={1/gm} m) =10K ohms w VB4 8xWL/LL 200 fF WL/LL I = gm Veff /2 = 10uA gm = 10ms, kpn = 150uA/ V^2 Ws/Ls >???? Lerr < 5.5% Werr < 0.24% 4xWL/LL 4xWS/LS Interdigitate 2 Inter digitate 4 VB4 {4xWL}/LL 10 uA/leg 10uA/leg \ I = 4/2 xWL/LL kp Veff^2 = 10uA WL/LL= VB1 4xWS/LS 4xWS/LS 4xWS/LS 4xWS/LS 4xWS/LS 4xWL/LL 10uA/leg 4xWS/LS {4xWL}/LL 4xWS/LS {Wmin}/LLmax VSS I R =Veff/ m) m=2 VDD > |VT| + 4Veff VB2 VB3 VB4 26 SOI Temperature Considerations Point 11--- What do you want at temperature? All regions • PTAT bias? • Constant gm • Constant Av or Constant Vpp Constant gain is not feasible in Subthreshold - VA/UT PTAT - provides constant gm or constant BW in Subthreshold. TnU Igm κ= but PTAT bias current in subthreshold is ⎟ ⎠ ⎞ ⎜ ⎝ ⎛⋅⎟ ⎠ ⎞ ⎜ ⎝ ⎛= Rf f I 2 1 TnULN R biased Square is constant gm or constant BW. What about Moderate inversion?? 4xWL/LL {mx4xWL}/LL I R = Veff2 /2 R =Veff/ m) R ={1/gm} m) =10K ohms w VB4 8xWL/LL 200 fF WL/LL I = gm Veff /2 = 10uA gm = 10ms, kpn = 150uA/ V^2 Ws/Ls >???? Lerr < 5.5% Werr < 0.24% 4xWL/LL 4xWS/LS Interdigitate 2 Inter digitate 4 VB4 {4xWL}/LL 10 uA/leg 10uA/leg \ I = 4/2 xWL/LL kp Veff^2 = 10uA WL/LL= VB1 4xWS/LS 4xWS/LS 4xWS/LS 4xWS/LS 4xWS/LS 4xWL/LL 10uA/leg 4xWS/LS {4xWL}/LL 4xWS/LS {Wmin}/LLmax VSS I R =Veff/ m) m=2 VDD > |VT| + 4Veff VB2 VB3 VB4 27 SOI Decouping of V Biases Point 12--- Be aware of slow bias nodes. All regions • "Slow is relative" • Add extra C - low Z long recovery • Active is best but not low power! o Nice use of low VT devices. Trim Pot Engineering