Homework 2 Problems with Solutions for Computer Organization | EE 3755, Assignments of Electrical and Electronics Engineering

Download Homework 2 Problems with Solutions for Computer Organization | EE 3755 and more Assignments Electrical and Electronics Engineering in PDF only on Docsity! EE 3755 Homework 2 Due: 22 February 2002 The solutions to the problems below are in the form of schematic diagrams. None of the problems include technol- ogy mapping. In each diagram be sure to label the module ports as they are labeled in the diagram to the right. a b ei eo Problem 1: Show the output, in the form of a schematic diagram showing gates, of the synthesizer inference step (before mapping and before optimization) for the module below (the solution to Homework 1, Problem 1). Hint: This is really easy. module decode_2_to_4(x0,x1,x2,x3,a); input [1:0] a; output x0, x1, x2, x3; not n0(a0n,a[0]); not n1(a1n,a[1]); and a0(x0,a1n,a0n); and a1(x1,a1n,a[0]); and a2(x2,a[1],a0n); and a3(x3,a[1],a[0]); endmodule Problem 2: Show the output of the synthesizer inference step for the module below (based on the solution to Homework 1, Problem 2). Show the adder as a module, not as individual gates. module atoi_implicit(i,s); input [7:0] s; output [3:0] i; assign i[3:0] = s[3:0] + ( s[6] ? 4’d9 : 4’d0 ); endmodule Problem 3: For the module above, show how the synthesizer might optimize the inferred hardware (but not the adder). Hint: using a pencil, draw four multiplexors, one for each bit. 1