Homework 5 Solutions - Introduction to Computer Architecture | CSE 141, Assignments of Computer Architecture and Organization

Download Homework 5 Solutions - Introduction to Computer Architecture | CSE 141 and more Assignments Computer Architecture and Organization in PDF only on Docsity! CSE141 Chien Homework #5 Solutions 12/03/2002 P&H Problem 7.7 1 is miss 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 4 is miss 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 4 8 is miss 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 4 8 5 is miss 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 4 5 8 20 is miss, replace 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 20 5 8 17 is miss. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 20 5 8 19 is miss. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 19 20 5 8 56 is miss, replace 8. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 19 20 5 56 9 is miss. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 19 20 5 56 9 11 is miss. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 19 20 5 56 9 11 4 is miss, replace 20. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 19 4 5 56 9 11 43 is miss, replace 11. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 19 4 5 56 9 43 5 is hit. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 19 4 5 56 9 43 6 is miss. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 19 4 5 6 56 9 43 9 is hit. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 19 4 5 6 56 9 43 17 is hit and this is the final contents of the cache. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 19 4 5 6 56 9 43 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8 56 9 17 19 1 1 4 20 5 43 is miss, replace 19. Set 0 1 2 3 4 5 6 7 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8 56 9 17 43 1 1 4 20 5 5 is hit. Set 0 1 2 3 4 5 6 7 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8 56 9 17 43 1 1 4 20 5 6 is m et 0 1 2 3 4 5 6 7 iss. S 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8 56 9 17 43 1 1 4 20 5 6 9 is hit. 5 6 7 Set 0 1 2 3 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8 56 9 17 43 1 1 4 20 5 6 17 is hit and this is the final contents of the cache. 1 2 3 4 5 6 7 Set 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8 56 9 17 43 1 1 4 20 5 6 Chien 12 The binary of 12, 16, 20, 76, 80, 84 are: 2: 0000 1100 0: 0001 0100 100 2 is a miss and is going to load 8-15 into cache block 001 and replace 72-79. 16-23 into cache block 010 and replace 80-87. is a hit. is a miss and is going to load 72-79 into cache block 001 and replace 8-15. lock 010 and replace 16-23. 4 is a hit. and is going to load 8-15 into cache block 1 of set 00. and is going to load 16-23 into cache block 1 of set 01. and is going to load 72-79 into cache block 2 of set 00. and is going to load 80-87 into cache block 1 of set 01. 2 is a hit. is a hit. is a hit. 4 is a hit. 1 16: 0001 0000 2 76: 0100 1100 80: 0101 0000 84: 0101 0 For directly mapped: 12 is a miss and is going to load 8-15 into cache block 001. 16 is a miss and is going to load 16-23 into cache 010. 20 is a hit. 76 is a miss and is going to load 72-79 into cache block 001 and replace 8-15. 80 is a miss and is going to load 80-87 into cache block 010 and replace 16-23. 84 is a hit. 1 16 is a miss and is going to load 20 76 80 is a miss and is going to load 80-87 into cache b 8 So the miss rate is 8/12 = 67% For 2-way set associative with LRU replacement : 12 is a miss 16 is a miss 20 is a hit. 76 is a miss 80 is a miss 84 is a hit. 1 16 is a hit. 20 76 80 is a hit. 8 So the miss rate is 4/12 = 33% Fully associative with LRU replacement : 12 is a miss and is going to load 8-15 into cache block 1. and is going to load 16-23 into cache block 2. and is going to load 72-79 into cache block 3. and is going to load 80-87 into cache block 4. 2 is a hit. is a hit. is a hit. seconds. conds ds econds. tal time 202.020002 seconds. ercentage of keyboard = 99.00% ercentage of CPU = 0% Percentage of Line printer = 1.00% Percentage of Floppy disk =0.0001% 16 is a miss 20 is a hit. 76 is a miss 80 is a miss 84 is a hit. 1 16 is a hit. 20 76 is a hit. 80 84 is a hit. So the miss rate is 4/12 = 33% Chien 13 According to figure 8.2, Time on keyboard is 2K/0.01 = 200 Time on CPU = 2 Micro se Time on Line printer = 2/1 = 2 secon Time on Floppy disk = 2/100 = 0.02 s To P P