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Parity Check Codes and CRC Error Detection Homework - Prof. Rudra Dutta, Assignments of Computer Systems Networking and Telecommunications

Homework problems related to parity check codes and crc error detection. Topics include generating parity bits, finding minimum distance, error probability, and designing convolutional coders. Students are required to find rules for generating parity bits, calculate codewords, and draw circuit diagrams.

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Pre 2010

Uploaded on 03/18/2009

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Download Parity Check Codes and CRC Error Detection Homework - Prof. Rudra Dutta and more Assignments Computer Systems Networking and Telecommunications in PDF only on Docsity! Homework 6 – CSC 570-001, Fall, 2004 Issued 10/15/04, due 10/21/04 All graded questions have equal weightage. 1. We saw in class that parity check codes can utilize multiple parity bits for a message by linearly combining (XORing) not all, but only some of the bits of the message. In this way, more than one parity bit can be generated for the same message. For example, the horizontal and vertical grid parity bit scheme generates each parity bit by considering only those bits on a particular row or column, after arranging the message bits on some sort of a grid. The other bits are not considered, for than particular parity bit. Consider a parity check code with three data bits and four parity bits, i.e. the code word looks like u2u1u0r3r2r1r0. Suppose that three of the codewords are 1001011, 1100110, and 0011110. By inspection, find the rule for generating each of the parity bits, write down all 8 codewords, and find the minimum distance of this code. 2. We saw that the grid parity scheme can be fooled by some 4-bit errors, but not all. If all bits have equal probability of being in error, and different bits being in error are independent events, then find the probability that a given 4-bit error goes undetected by the scheme. Assume that the dataword is mn bits long, and these bits are arranged in m columns and n rows to form the grid. 3. Consider the order in which message bits are arranged in the grid. (a) With the above assumption with respect to the bit errors, does a difference in order make any difference to the error control strength of the code? (Of course, whatever order is used will have to be agreed upon by the sender and receiver side error control algorithms, otherwise nothing works.) (b) Now consider burst errors. Specifically, assume that 1-, 2- and 3-bit errors can occur anywhere in the message, but a 4-bit error can only occur if the four bits form a 4-bit burst. Assume that more than 4 bits are never in error. Can the ordering of the message bits into the grid affect the strength of the code, given this knowledge? 4. (a) Quote the generator polynomial used to generate the CRC code in the IEEE 802.3 standard, providing page and paragraph references. (b) Encode the message u = 10010110100111010101010101001010010100000 using the above generator polynomial (simply perform the CRC, do not perform the 32 bit inversions that 802.3 specifies) by using the long division method. (c) Draw the circuit for the corresponding shift register. (d) Trace the operation of the shift register by drawing a table as we did in the relevant lecture slide, and show that the same CRC is obtained. Note: For part (d) only, it is fine to obtain the table by writing a simple computer program and attaching the printout. Please only use code you have written yourself, not code from a classmate or off the web somewhere. 5. We performed maximum likelihood detection for the convolution code specified in the lecture using the decode trellis in class. Do the same for each of the following received strings. You can assume that the state machine started in state ‘00’, but not that it ended up in that state. (a)1110010101101010
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