Download Homework 6 Solutions - Computer Architecture | ELEC 5200 and more Assignments Computer Architecture and Organization in PDF only on Docsity! ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2008 Homework 6 Solution Assigned 10/6/07, due 10/13/07 Problem 1: Consider two types of MIPS datapaths. The clock rates for single-cycle and multicycle implementations are 250MHz and 1GHz, respectively. The following subroutine is used for estimating the performances. The argument register $a0 contains a very large positive integer (a million or greater: repeat beq $a0, $zero, finish beq $a0, $zero, finish beq $a0, $zero, finish addi $a0, $a0, –1 jump repeat finish add $v0, $a0, $zero Determine: (a) Average cycles per instruction (CPI) for two datapaths. (b) How much faster is the multicycle execution of the program (ratio of single-cycle to multicycle execution times)? Answer: (a) Single-cycle CPI = 1.0, because each instruction executes in one cycle. The instructions from repeat to jump are executed a0 (several million) times. Therefore, we neglect the two add instructions preceding repeat and finish, which are executed only one time each. Thus, the instruction mix for multicycle datapath is: beq takes 3 cycles and is executed 3a0+1≈3a0 times. jump takes 3 cycles and is executed a0 times. add and addi each takes 4 cycles; add is executed once (neglected) and addi is executed a0 times. Multicycle CPI = (3×3 + 3×1 + 4×1)/(3 + 1 + 1) = 16/5 = 3.2 (b) The multicycle clock period is 1ns and the single-cycle clock period is 4ns. Therefore, Performance ratio = (single-cycle time)/(multicycle time) = 4/(1×3.2) = 1.25 Problem 2: Sketch a schematic showing a multicycle MIPS datapath for the execution of the jump and link (jal) instruction. In your schematic you may include only those units that participate in the execution of this instruction. Answer: The MIPS jal instruction (opcode = 000011) does two things: 1. Writes PC+4 in the return address register ra (#31 in register file). 2. Multiply the 26-bit argument by 4 (i.e., shift left 2), insert four leading bits from PC, and place the result in PC. Sequence of operations: Following sketch shows the data paths set up for execution of the jal instruction. Several multiplexers controlled by the control FSM are not shown for clarity: Cycle 1: PC supplies address to memory, which outputs instruction word to instruction register. Constant 4 is added to PC and result is written back into PC. Cycle 2: Bits 26-31 (opcode) of instruction register are decoded by control FSM, which advances to jump state in the next clock cycle. Cycle 3: Content of PC is written to register #31 of register file. Bits 0-25 of instruction register are left shifted by 2, four MSBs from PC are concatenated and the resulting 32 bits are written to PC. Control FSM advances to fetch state in the next clock cycle. 6 26 add 4 rtMem. P C ALUOut Reg. 31 I n st . R e g Reg. file Bits 26-31 to control FSM Left shift by 2 28 4 MSBs 32 ALU
