Computer Architecture and Design Homework 7 Solutions: Cache Access Time and Locality - Pr, Assignments of Computer Architecture and Organization

Download Computer Architecture and Design Homework 7 Solutions: Cache Access Time and Locality - Pr and more Assignments Computer Architecture and Organization in PDF only on Docsity! ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2009 Homework 7 Solution Assigned 4/10/09, due 4/17/09 Problem 1: To meet the data access time requirement a one-level SRAM cache must have a 97% hit rate. However, high cost of SRAM forces us to use a smaller size for which hit rate is 90%. Thus, the access time of one-level cache will exceed the required limit. We add a level-2 DRAM cache to bring the access time to the required value. (a) Show that the cycle time of the L2 DRAM cache must not exceed 30% that of the main memory. (b) Show that the hit rate of L2 cache must not be less than 70%. (c) If the cycle time of the L2 cache DRAM is 10% that of the main memory cycle time, then what should be the minimum hit rate of the L2 cache? Problem 2: Derive the following formula for the access time of a K level cache: K Access time, t(K) = TM Σ ( rK-i mi ) cycles i=0 Where TM is the hardware cycle time of the main memory in clock cycles m is the miss rate (assumed the same) for all caches (m << 1.0) r is the ratio (assumed the same) of cycle times for any two consecutive caches. For example, T1/T2 = r, and TK/TM = r. Clearly, r < 1.0, because caches become progressively faster as we move from the main memory toward processor. Verify the formula for K = 0 (no cache), 1, 2, 3, and any other value, K = ∞ ? [Hint: One possible way to derive the formula is to repeatedly use the one level cache formula.] Problem 3: Suppose we model the influence of physical clustering of data in memory on the cache by a locality parameter C, 0 < C ≤ 1, such that the hit ratio is expressed as h = (m/M)C, where m is the size of the one-level cache and M that of the main memory. Assuming that the cycle time of memory hardware reduces in proportion to the size of the memory, determine the cache size that will minimize the average data access time. Find cache sizes and hit rates for highly localized (C << 1) and highly unclustered (C ≈ 1) data. Problem 4: Examine the paper: K. Beyls and E. H. D'Hollander, "Refactoring for Data Locality," Computer, vol. 42, no. 2, pp. 62-71, February 2009, and give an example of code modification that could improve the cache performance.