Homework #8 with Solutions - Microelectronic Circuits | ECE 3040, Assignments of Electrical and Electronics Engineering

Download Homework #8 with Solutions - Microelectronic Circuits | ECE 3040 and more Assignments Electrical and Electronics Engineering in PDF only on Docsity! ECE 3040B Homework 8 Solutions 1.) Jaeger 13.17 2.) Jaeger 13.23 3.) Jaeger 13.90 Plus, solve for the input and output resistances. 5.) a.) Use ideal opamps to design a filter (show work) that has 2 zeros at DC, and poles at 100 Hz, 10KHz, and 500 kHz and to have a bandpass gain of 1000 v/v. b.) Simulate this filter in PSPICE using ideal voltage controlled voltage amplifiers (setting gain to ~1e9). Plot the 20xLOG(Voltage Gain) verses Log(frequency) up to 10 MHz. c.) Simulate this filter in PSPICE using the u741 Operational amplifier model. Plot the 20xLOG(Voltage Gain) verses Log(frequency) up to 10 MHz. d.) Explain the differences between your results in b and c. Note: Sample lowpass filter circuits are available on the web page illustrating how to model the op amps. Since each basic high pass filter has a zero at DC and a pole, and each basic low pass filter has only one pole, we need 2 high pass stages and one low pass stage. Noting as was done in the notes that we can use a bandpass configuration to combine the low and high pass functions around one op-amp, we can perform this operation with only 2 op-amps. Generally, to preserve the “pass-band gain” at the desired 1000 v/v (or 60 dB), we need to have our lowest and highest “break frequencies” (the frequencies where the slope of the Bode Plot changes) in our first stage. Otherwise, the first stage will be reducing the gain in frequency ranges where the second stage is trying to amplify the signal. Thus, the circuit on the next page is our solution. This circuit’s transfer function is:       +       +       + = sCR sCR sCRsCR sCR Vin Vout 33 34 2211 12 11 1 1 where the first term is the high pass filter of the first op-amp (E1, or U1), the second term is the low pass filter of the first op-amp (E1, or U1), and the last term is the high pass filter of the second op-amp (E2, or U2). This function implements the zeros at DC due to the s2 term in the numerator. I will choose to give (free choice) 20 dB of gain (10 V/V) in the first stage, and 40 dB of gain (100 V/V) in the second stage for a total gain of 60 dB (1000 V/V). This sets the ratio of resistors as: 10010 3 4 1 2 == R R and R R due to the desired “pass-band gain” constraints . Now we can set our frequencies: 33 10@ 2122 500@ 11 100@ 2 1 20 1 2 1 2 1 CR f CRCR f CR f kHzpole kHzpole Hzpole π ππ π = == = Beyond these limitations (and practical limits of resistor and capacitor choices), we are free to choose parameters at will. The values below satisfy all of these constraints: R1=1K, R2=10K, R3=10K, R4=1Meg, C1=1.59uF, C2=31.9pF, and C3=1.59nF b.) The Bode Plot of the gain simulation from PSPICE of each stage (stage 1 is for E1, or U1 and stage 2 is for E2, or U2) is shown on the page following the circuit diagram. Note that the slope of the Bode Plot starts out at +40 dB per decade due to the existence of 2 zeros at DC. After the first pole at 100 Hz (set by stage 1), the slope reduces to +20 dB/decade. After the second pole at 10 kHz (set by stage 2) the slope is zero. After the last pole at 500 kHz (set by stage 1), the slope is – 20 dB/decade. Also note that stage 2 implements the high pass function while stage 1 implements the bandpass function. The pass-band gain is correct at 60 dB (or 1000 V/V). c.) The circuit using the ua741 op-amp is shown on a following page. Note that the model for the ua741 op-amp does require us to include the power supply voltage sources. Otherwise everything is identical to the previous circuit from parts a and b. The Bode Plot for this circuit is shown on a following page. The lower frequency response (~<10kHz) behaves identically to that of the ideal case. However, the frequency response at high frequencies is severely degraded resulting in gain that falls off faster than the expected –20 dB/decade. d.) The rapid decrease in the high frequency gain results from the finite “Gain-Bandwidth” of the ua741. Further incite into this problem: Since the gain begins to role off somewhere around ~100 kHz for stage 1 which has a gain of 10, we can estimate the gain-bandwidth product to be (10 v/v)(100kHz)=1,00,000 Hz. We can check this calculation by using the unity gain (follower) circuit shown on a following page. The Bode Plot for this circuit is also shown. From this figure we clearly see that the gain drops by –3dB at ~1MHz confirming our calculation. This concept of gain effecting frequency response is also shown in the last Bode Plot for this problem for 3 standard non-inverting amplifiers with gains of 101, 1001 and 10,001 V/V. Note the lower frequency response for the higher gain circuit. All of these gain responses converge to the open loop frequency response for the ua741 (not shown). [et b.) VDE C3. ¢ _F* ) Vout pe &| 4 f tT) 199n GaIn=ié9 | | R4 = gv aif 1Meg E3 Vstage2only + = | VDB This part of the Circuit is for demonstration and is not part of the Solusion  6Q'CO TT 'autL 1 afeq Wee ‘Pe Ttady :saeq Aauanbezg (ATUOTABeISA) ATA © (ANCA) EAA & 2HHOT 2HHO*T ZHMOOT ZHIOT 2HAO'T 2HOOT 2HOT 2HO'T - + O8- epelsp/ep ‘ or- ribee a ‘@seo Teepy oa oa pexedus papeaiep aoueuzozzed Aoua > koe . ' { ' aus = «08 Jeep qt#syzomeuoH (¥) O°LZ teinjereduag TOI Fe‘ PO tuna Surry /ezeq YOST HEX TOMAWOH\ S3>eCoI1g\g AgWTSH\ IO  * C:\MSimEv_8\Projects\Homeworké#1c.sch Temperature: 27.0 Date/Time run: 04/24/101 12:26:56 So 7 ee; , 27.0 (A) Homework@#le.dat 10 7 01 fe ee Fone eee Bo F Unity Gain Buffer Frequency Response -104 -20 ' -304 : =a0} . sara rr sorte 1,OHZ 10Hz 100Hz 1. 0KH2 10KHz 1OOKHz 1 VOB(Vout) L Frequency cancers | Date: April 24, 2001 Page 1 Time: 12:29:26