Homework I Solutions - Advanced Computer Architecture | CSCI 5593, Assignments of Computer Architecture and Organization

Download Homework I Solutions - Advanced Computer Architecture | CSCI 5593 and more Assignments Computer Architecture and Organization in PDF only on Docsity! Homework 1 Solutions Dirk Grunwald – CSCI 5593 1. Solve problem #1.1 - this problem concerns Amdahls law and vectorization. We know that the maximum speedup possible from the vector optimization is 20; the exercise asks for the level of vectorization needed to each 1/2 of the maximum speedup. We take amdahls equation (1.1) and solve for fraction enhanced: Speeduporiginal

 Fractionenhanced    Fractionenhanced  Speedupenhanced  Fractionenhanced Speedupenhanced  Speeduporiginal 
 Speeduporiginal  Speedupenhanced 
 We then plug in the values we were give (Speedupenhanced  Speeduporiginal
 and get the value   . 2. Solve Problem #1.5 Assume we have a machine that, with a perfect cache, behaves like this: Inst. Type Frequency Clock Cycle Count ALU 43% 1 Loads 21% 2 Stores 12% 2 Branches 24% 2 With a cache, instructions have a miss rate of 5%, data references have a miss rate of 10% and the miss penalty is 40 cycles. Find the CPI for each instruction class with the cache misses and determine how much faster the machine is without any cache misses vs with cache misses. Ok - the first thing to do is determine the CPI of each instruction class with cache misses. Instruction execution can be broken down into instruction fetch and execution. The table shows us normal execution execution delay. Not all the instructions access data – only load and store access data and thus only they can suffer from a data cache miss. The possible stall due to an instruction cache miss is  , or 2 cycles on average. The possible stall due to a data cache miss is
 , or 4 cycles. We’ll calculate the CPI for each instruction class using this relationship: ! #"%$'&(&)  Accesses *)+ +, Frequency *)+ +  Penalty *-+ +    Accesses . $/"%$  Frequency . $/"%$  Penalty . $/"%$  and   *-.'0 $'&  ! 1"%$/&(&) . This means we’ve got the following CPI’s: Inst. Type Frequency  *2.'0 $/& Perfect Cache Real Cache #"%$/&(&- CPI  #"%$/&3&) CPI ALU 43% 1 0 1 2 3 Loads 21% 2 0 2 2 + 4 8 Stores 12% 2 0 2 2 + 4 8 Branches 24% 2 0 2 2 4 1 To find the overall CPI, we multiply by the fraction of execution type. 54 016/780:9 "
;<    
   
      =
 > 650 $'& ;?;< @  
 A@ 
   ?  =    This means the speedup is BDCE8E8FGC HIKJ#L#MONQPHRIKJTS MTL1MTU%LOV XWZY [\ Y ] ; 
. 3. Solve Problem #1.13 (a) Obviously, ^  B Instruction CountExecution Time _ \:`/a . If the program executes b floating point instructions, and it takes c integer instructions to emulate those instructions, than the MIPS rating for the original machine is^ d BKeQ65*)f J/gRh _jik _ \:` a and that for the accelerated machine is ^ d B $ 91910 & J/g il _ \:` a . (b) We plug in ^ d B ej6j*)f   c mbn 
] ^  BKej65*3fm n 
] o  cmb  
p q
] r    @ 
]  @ 
] or 80 million instructions. (c) The value of B is ^  B $ 91910 &   bs 
]s   b^t
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seconds (d) The ^ubvw  B yx _ \:` a\ Y \ = 7.27MF. (e) Yes, the system should be purchased because it finishes the job in 1.1 seconds rather than 4. This means it is 3.6 times faster than the single workstation. 4. Solve Problem #2.3 See Table [?] for the code fragments and accounting of program size. The memory-memory design has the most compact program representation, but also references the most memory. The load-store architecture references the least memory, but has a large program size. If you had a 32-bit address space, you’d find that the load-store design begins to have more advantages in code space since it can use “short names” (registers) more often. 5. Solve Problem #2.6 This is the most straight-forward translation. This is what you would expect from an exceptionally bad compiler (e.g. gcc with -O0, which disables all optimization). ex2_6: addi r1,r0,#1 ; init i sw 2000(r0),r1 ; store i 2