VHDL Homework Announcements: Chapter 5 Quiz, Quartus II Assignment, and Homework #8 - Prof, Assignments of Electrical and Electronics Engineering

Download VHDL Homework Announcements: Chapter 5 Quiz, Quartus II Assignment, and Homework #8 - Prof and more Assignments Electrical and Electronics Engineering in PDF only on Docsity! Announcements • Homework #8 • Read Chapter 5: Sections 1 and 4 • Chapter 5 Online Quiz (Due by Midnight Wed 3/17) • Quartus II Assignment: Due by 8:45am on Thursday, 3/18 – May work with a partner. – See website for Quartus II VHDL submission requirements • 8A) Obtain five equations from VHDL Boolean Algebra online quiz – Implement the original equations using VHDL (do not minimize( • See Blackboard for VHDL template Announcements • Homework #8b – Using VHDL design a circuit which implements the following function – Y=Ax2 +Bx + C • Where A, B and C are given in the Parameter Table below – Design two circuits • Circuit 1: X is a three-bit unsigned vector • Circuit 2: X is a three-bit signed vector – Let Y (signed) be as wide as needed to cover desired range. – If working with a partner, use one partner’s last name for Circuit 1, the other last name for Circuit 2. Clearly indicate which name is being used with which circuit. – This can be the EXACT same circuit you used for HW#7