Download In-order vs. Out-of-order Execution and more Exercises Computer Architecture and Organization in PDF only on Docsity! 1 Spring 2006 CSE 471 -- Introduction to Out-of- Order Execution 1 In-order vs. Out-of-order Execution In-order instruction execution • instructions are fetched, executed & completed in compiler- generated order • one stalls, they all stall • instructions are statically scheduled Out-of-order instruction execution • instructions are fetched in compiler-generated order • instruction completion may be in-order (today) or out-of-order (older computers) • in between they may be executed in some other order • independent instructions behind a stalled instruction can pass it • instructions are dynamically scheduled Spring 2006 CSE 471 -- Introduction to Out-of- Order Execution 2 Dynamic Scheduling Out-of-order processors: • after instruction decode • check for structural hazards • an instruction can be issued when a functional unit is available • an instruction stalls if no appropriate functional unit • check for data hazards • an instruction can execute when its operands have been calculated or loaded from memory • an instruction stalls if operands are not available 2 Spring 2006 CSE 471 -- Introduction to Out-of- Order Execution 3 Dynamic Scheduling Out-of-order processors: • don’t wait for previous instructions to execute if this instruction does not depend on them, i.e., independent ready instructions can execute before earlier instructions that are stalled • case 1: stalled load has missed in a cache • when independent instructions go around a load • use lockup-free caches that allow instruction issue to continue while a miss is being satisfied • the load-use instruction still stalls Spring 2006 CSE 471 -- Introduction to Out-of- Order Execution 4 Dynamic Scheduling in-order processors lw $3, 100($4) in execution, cache miss add $2, $3, $4 waits until the miss is satisfied sub $5, $6, $7 waits for the add out-of-order processors lw $3, 100($4) in execution, cache miss sub $5, $6, $7 can execute during the cache miss add $2, $3, $4 waits until the miss is satisfied
