I/O Module Function and Techniques in Computer Architecture - Prof. David L. Tarnoff, Exams of Computer Architecture and Organization

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Tarnoff and more Exams Computer Architecture and Organization in PDF only on Docsity! 1 Input/Output– Page 1 of 51CSCI 4717 – Computer Architecture CSCI 4717/5717 Computer Architecture Topic: Input/Output Reading: Stallings, Chapter 7 Input/Output– Page 2 of 51CSCI 4717 – Computer Architecture General Description of I/O Wide variety of peripherals • Delivering different amounts of data • At different speeds • In different formats (bit depth, etc.) Input/Output– Page 3 of 51CSCI 4717 – Computer Architecture Closing the Gap • Need I/O modules to act as bridge between processor/memory bus and the peripherals Processor Bus I/O Module External sensors and controls Device Interface Device Interface Device Interface Input/Output– Page 4 of 51CSCI 4717 – Computer Architecture External Devices • External devices are needed as a means of communication to the outside world (both input and output – I/O) • Types – Human readable – communication with user (monitor, printer, keyboard, mouse) – Machine readable – communication with equipment (hard drive, CDROM, sensors, and actuators) – Communication – communication with remote computers/devices (Can be any of the first two or a network interface card or modem) Input/Output– Page 5 of 51CSCI 4717 – Computer Architecture Generic Device Interface Configuration Input/Output– Page 6 of 51CSCI 4717 – Computer Architecture Device Interface Components • The control logic is the I/O module's interface to the device • The data channel passes the collected data from or the data to be output to the device. On the opposite end is the I/O module, but eventually it is the processor. • The transducer acts as a converter between the digital data of the I/O module and the signals of the outside world. – Keyboard converts motion of key into data representing key pressed or released – Temperature sensor converts amount of heat into a digital value – Disk drive converts data to electronic signals for controlling the read/write head 2 Input/Output– Page 7 of 51CSCI 4717 – Computer Architecture I/O Module Functions • Control & Timing • Processor Communication • Device Communication • Data Buffering • Error Detection Input/Output– Page 8 of 51CSCI 4717 – Computer Architecture I/O Module: Control and Timing • Required because of multiple devices all communicating on the same channel • Example – CPU checks I/O module device status – I/O module returns status – If ready, CPU requests data transfer – I/O module gets data from device – I/O module transfers data to CPU – Variations for output, DMA, etc. Input/Output– Page 9 of 51CSCI 4717 – Computer Architecture I/O Module: Processor Communication • Commands from processor – Examples: READ SECTOR, WRITE SECTOR, SEEK track number, and SCAN record ID. • Data – passed back and forth over the data bus • Status reporting – Request from the processor for the I/O Module's status. May be as simple as BUSY and READY • Address recognition – I/O device is setup as a block of one or more addresses unique to itself Input/Output– Page 10 of 51CSCI 4717 – Computer Architecture Other I/O Module Functions • Device Communication – specific to each device • Data Buffering – Due to the differences in speed (device is usually orders of magnitude slower) the I/O module needs to buffer data to keep from tying up the CPU's bus with slow reads or writes • Error Detection – simply distributing the need for watching for errors to the module. They may include: – Malfunctions by device (paper jam) – Data errors (parity checking at the device level) – Internal errors to the I/O module such as buffer overruns Input/Output– Page 11 of 51CSCI 4717 – Computer Architecture I/O Module Structure Input/Output– Page 12 of 51CSCI 4717 – Computer Architecture I/O Module Level of Operation • How much control will the CPU be required to handle? • How much will the CPU be allowed to handle? • What will the interface look like, e.g., Unix treats everything like a file • Support multiple or single device • Will additional control be needed for multiple devices on a single port (e.g., serial port versus USB) 5 Input/Output– Page 25 of 51CSCI 4717 – Computer Architecture CPU Viewpoint Input/Output– Page 26 of 51CSCI 4717 – Computer Architecture CPU Viewpoint (continued) • Issue read command Do other work • Check for interrupt at end of each instruction cycle (NO CODE IS INVOLVED IN THIS) • I/O module issues interrupt request Input/Output– Page 27 of 51CSCI 4717 – Computer Architecture CPU Viewpoint (continued) I/O module issues interrupt request forcing processor to: • Save context on stack – Registers (this may have to be done by ISR) – Pointers including PC/IP, but not SP – Flags (Program Status Word) • Send acknowledgement so I/O module can release request • Process interrupt by loading address of ISR into PC/IP • Interrupt must save results of ISR because more than likely, returning from the interrupt will erase all indications that it happened at all • Retrieve context including PC/IP Input/Output– Page 28 of 51CSCI 4717 – Computer Architecture Interrupt I/O Example (continued from programmed I/O) Control: • Transmit interrupt enable (TIE) – set to one enables interrupt when TDRE is set to one • Transmit complete interrupt enable (TCIE) – set to one enables interrupt when TC is set to one • Receive interrupt enable (RIE) – set to one enables interrupt when RDRF is set to one or when error occurs Input/Output– Page 29 of 51CSCI 4717 – Computer Architecture Interrupt I/O Example (continued) Status: • Overrun error (OR) – set to one when character received but there was no room in SCDR • Noise flag (NF) – set to one when noise is detected on receive input • Framing error (FE) – set to one when received data had error with framing bits Input/Output– Page 30 of 51CSCI 4717 – Computer Architecture Interrupt I/O Example (continued) “Transmitting a character” SCCR2 |=0x88; // Set TIE and TE to 1 setISR(&ser_tx_ISR()); // At this point, processor can do something else void INTERRUPT ser_tx_ISR() { SCDR = next_byte_to_send; } 6 Input/Output– Page 31 of 51CSCI 4717 – Computer Architecture Interrupt I/O Example (continued) “Receiving a character” SCCR2 |=0x24; // Set RIE and RE to 1 setISR(&ser_rx_ISR()); // At this point, processor can do something else void INTERRUPT ser_rx_ISR() { if ((SCSR & 0x2E) == 0x20) received_byte = SCDR; else if ((SCSR & 0xE) != 0) process_error(); } Input/Output– Page 32 of 51CSCI 4717 – Computer Architecture Design Issues • Resolution of multiple interrupts – How do you identify the module issuing the interrupt? • Priority – How do you deal with multiple interrupts at the same time or interrupting in the middle of an interrupt? Input/Output– Page 33 of 51CSCI 4717 – Computer Architecture Identifying Interrupting Module • Different interrupt line for each module • Limits number of devices • Even with this method, there are often multiple interrupts still on a single interrupt lined • Priority is set by hardware Input/Output– Page 34 of 51CSCI 4717 – Computer Architecture Software poll • Single interrupt line – when interrupt occurs, CPU then goes out to check who needs attention • Slow • Priority is set by order in which CPU polls devices Input/Output– Page 35 of 51CSCI 4717 – Computer Architecture Daisy Chain or Hardware poll • Interrupt Acknowledge sent down a chain • Module responsible places unique vector on bus • CPU uses vector to identify handler routine • Priority is set by order in which interrupt acknowledge gets to I/O modules, i.e., order of devices on the chain Input/Output– Page 36 of 51CSCI 4717 – Computer Architecture Bus Arbitration • Allow multiple modules to control bus (See “Method of Arbitration,” p. 75) • I/O Module must claim the bus before it can raise interrupt • Can do this with: – Bus controller/arbiter – Distribute control to devices • Must be one master, either processor or other device • Device that "wins" places vector on bus uniquely identifying interrupt • Priority is set by priority in arbitration, i.e., whoever is currently in control of the bus 7 Input/Output– Page 37 of 51CSCI 4717 – Computer Architecture Example: 82C59A (Fig. 7.9) Input/Output– Page 38 of 51CSCI 4717 – Computer Architecture 82C59A (continued) • 80386 has one interrupt line • 8259A has 8 interrupt lines Input/Output– Page 39 of 51CSCI 4717 – Computer Architecture 82C59A Sequence of Events • 82C59A accepts interrupts • 82C59A determines priority – Fully nested IR0 (highest) through IR7 (lowest) – Rotating – after interrupt is serviced, it goes to bottom of priority list – Special mask – allows individual interrupts to be disabled • 82C59A signals 8086 (raises INTR line) • CPU Acknowledges with INTA line • 82C59A puts correct vector on data bus • CPU processes interrupt Input/Output– Page 40 of 51CSCI 4717 – Computer Architecture Direct Memory Access (DMA) • Impetus behind DMA – Interrupt driven and programmed I/O require active CPU intervention (All data must pass through CPU) • Transfer rate is limited by processor's ability to service the device • CPU is tied up managing I/O transfer Input/Output– Page 41 of 51CSCI 4717 – Computer Architecture DMA (continued) • Additional Module (hardware) on bus • DMA controller takes over bus from CPU for I/O – Waiting for a time when the processor doesn't need bus – Cycle stealing – seizing bus from CPU (more common) Input/Output– Page 42 of 51CSCI 4717 – Computer Architecture DMA Operation • CPU tells DMA controller: – whether it will be a read or write operation – the address of device to transfer data from – the starting address of memory block for the data transfer – the amount of data to be transferred • DMA performs transfer while CPU does other processes • DMA sends interrupt when completed