input output in computer arc and org, Slides of Computer Architecture and Organization

Download input output in computer arc and org and more Slides Computer Architecture and Organization in PDF only on Docsity! + Input/Output 1 + Overview 2 + External Devices ◼ Provide a means of exchanging data between the external environment and the computer ◼ Attach to the computer by a link to an I/O module ◼ The link is used to exchange control, status, and data between the I/O module and the external device ◼ Peripheral device ◼ An external device connected to an I/O module Three categories: ◼ Human readable ◼ Suitable for communicating with the computer user ◼ Video display terminals (VDTs), printers ◼ Machine readable ◼ Suitable for communicating with equipment ◼ Magnetic disk and tape systems, sensors and actuators ◼ Communication ◼ Suitable for communicating with remote devices such as a terminal, a machine readable device, or another computer 5 Buffer Transducer Figure 7.2 Block Diagram of an External Device Control Logic Control signals from I/O module Status signals to I/O module Data bits to and from I/O module Data (device-unique) to and from environment 6 + Keyboard/Monitor ◼ Basic unit of exchange is the character ◼ Associated with each character is a code ◼ Each character in this code is represented by a unique 7-bit binary code ◼ 128 different characters can be represented ◼ Characters are of two types: ◼ Printable ◼ Alphabetic, numeric, and special characters that can be printed on paper or displayed on a screen ◼ Control ◼ Have to do with controlling the printing or displaying of characters ◼ Example is carriage return ◼ Other control characters are concerned with communications procedures Keyboard (Input) ◼ When the user depresses a key it generates an electronic signal that is interpreted by the transducer in the keyboard and translated into the bit pattern of the corresponding IRA code ◼ This bit pattern is transmitted to the I/O module in the computer Monitor (Output) ◼ On output, IRA code characters are transmitted to an external device from the I/O module ◼ The transducer interprets the code and sends the required electronic signals to the output device either to display the indicated character or perform the requested control function International Reference Alphabet (IRA) Most common means of computer/user interaction User provides input through the keyboard The monitor displays data provided by the computer 7 + I/O Module Decisions • I/O module may hide the details of timing, formats, and the electro-mechanics of an external device so that the processor can function in terms of simple read and write commands, and possibly open and close file commands. I/O channel or I/O processor • An I/O module that takes on most of the detailed processing burden, presenting a high-level interface to the processor (MainFrames) I/O controller or Device controller • An I/O module that is quite primitive and requires detailed control (Microcomputers) 10 + Input Output Techniques 11 + I/O Techniques Three techniques are possible for I/O operations: ◼ Programmed I/O ◼ Data are exchanged between the processor and the I/O module ◼ Processor executes a program that gives it direct control of the I/O operation ◼ When the processor issues a command it must wait until the I/O operation is complete ◼ If the processor is faster than the I/O module this is wasteful of processor time ◼ Interrupt-driven I/O ◼ Processor issues an I/O command, continues to execute other instructions, and is interrupted by the I/O module when the latter has completed its work ◼ Direct memory access (DMA) ◼ The I/O module and main memory exchange data directly without processor involvement 12 + I/O Commands ◼ There are four types of I/O commands that an I/O module may receive when it is addressed by a processor: 1) Control - used to activate a peripheral and tell it what to do 2) Test - used to test various status conditions associated with an I/O module and its peripherals 3) Read - causes the I/O module to obtain an item of data from the peripheral and place it in an internal buffer 4) Write - causes the I/O module to take an item of data from the data bus and subsequently transmit that data item to the peripheral 15 + I/O Mapping Summary ◼ Memory mapped I/O ◼ Devices and memory share an address space ◼ I/O looks just like memory read/write ◼ No special commands for I/O ◼ Large selection of memory access commands available ◼ Isolated I/O ◼ Separate address spaces ◼ Need I/O or memory select lines ◼ Special commands for I/O ◼ Limited set 16 Interrupt-Driven I/O The problem with programmed I/O is that the processor has to wait a long time for the I/O module to be ready for either reception or transmission of data An alternative is for the processor to issue an I/O command to a module and then go on to do some other useful work The I/O module will then interrupt the processor to request service when it is ready to exchange data with the processor The processor executes the data transfer and resumes its former processing 17 Start N + 1 Y + L N Y Y T Return User's Program Main Memory Processor General Registers Program Counter Stack Pointer N + 1 T – M T – M T Control Stack Interrupt Service Routine User's Program Interrupt Service Routine (a) Interrupt occurs after instruction at location N (b) Return from interrupt Figure 7.7 Changes in Memory and Registers for an Interrupt Start N + 1 Y + L N Y T Return Main Memory Processor General Registers Program Counter Stack Pointer Y + L T – M T – M T Control Stack N + 1 20 1 2 3 5 Two design issues arise in implementing interrupt I/O: • Because there will be multiple I/O modules how does the processor determine which device issued the interrupt? • If multiple interrupts have occurred how does the processor decide which one to process? Design Issues 21 + Device Identification ◼ Multiple interrupt lines ◼ Between the processor and the I/O modules ◼ Most straightforward approach to the problem ◼ Consequently even if multiple lines are used, it is likely that each line will have multiple I/O modules attached to it ◼ Software poll ◼ When processor detects an interrupt it branches to an interrupt-service routine whose job is to poll each I/O module to determine which module caused the interrupt ◼ Time consuming ◼ Daisy chain (hardware poll, vectored) ◼ The interrupt acknowledge line is daisy chained through the modules ◼ Vector – address of the I/O module or some other unique identifier ◼ Vectored interrupt – processor uses the vector as a pointer to the appropriate device-service routine, avoiding the need to execute a general interrupt-service routine first ◼ Bus arbitration (vectored) ◼ An I/O module must first gain control of the bus before it can raise the interrupt request line ◼ When the processor detects the interrupt it responds on the interrupt acknowledge line ◼ Then the requesting module places its vector on the data lines Four general categories of techniques are in common use: 22 Address register Control logic Data register Figure 7.12 Typical DMA Block Diagram Data count Data lines Address lines Request to DMA Acknowledge from DMA Interrupt Read Write 25 + DMA Transfer - Cycle Stealing • DMA controller takes over bus for a cycle • Transfer of one word of data • Not an interrupt ◼ CPU does not switch context, pauses for one bus cycle • CPU suspended just before it accesses bus ◼ i.e. before an operand or data fetch or a data write • Slows down CPU but not as much as CPU doing transfer 26 Processor Cycle Fetch Instruction Processor Cycle Decode Instruction Processor Cycle Instruction Cycle Time DMA Breakpoints Figure 7.13 DMA and Interrupt Breakpoints During an Instruction Cycle Interrupt Breakpoint Fetch Operand Processor Cycle Execute Instruction Processor Cycle Store Result Processor Cycle Process Interrupt 27 + Characteristics of I/O Channels ◼ The I/O channel represents an extension of the DMA concept. An I/O channel has the ability to execute I/O instructions, which gives it complete control over I/O operations. ◼ In a computer system with such devices, the CPU does not execute I/O instructions. Such instructions are stored in main memory to be executed by a special-purpose processor in the I/O channel itself. ◼ Thus, the CPU initiates an I/O transfer by instructing the I/O channel to execute a program in memory. ◼ The program will specify the device or devices, the area or areas of memory for storage, priority, and actions to be taken for certain error conditions. ◼ The I/O channel follows these instructions and controls the data transfer. 30 + Types of Interfaces ◼ In a Parallel interface, there are multiple lines connecting the I/O module and the peripheral, and multiple bits are transferred simultaneously, just as all of the bits of a word are transferred simultaneously over the data bus. ◼ In a Serial interface, there is only one line used to transmit data, and bits must be transmitted one at a time. ◼ With a new generation of high-speed serial interfaces, parallel interfaces are becoming much less common. 31 : Parallel and Serial I/O | LO module - To system LTT TITTTT 1 To bus Buffer peripheral —_—_— > (a) Parallel VO LO module To To system CLIT TTT) . ie Buffer peripheral ———— $$ (b) Serial VO + FireWire Serial Bus ◼ Was developed as an alternative to small computer system interface (SCSI) to be used on smaller systems, such as personal computers, workstations, and servers ◼ Objective was to meet the increasing demands for high I/O rates while avoiding the bulky and expensive I/O channel technologies developed for mainframe and supercomputer systems ◼ IEEE standard 1394, for a High Performance Serial Bus ◼ Uses a daisy chain configuration, with up to 63 devices connected off a single port ◼ 1022 FireWire buses can be interconnected using bridges ◼ Provides for hot plugging which makes it possible to connect and disconnect peripherals without having to power the computer system down or reconfigure the system ◼ Provides for automatic configuration ◼ No terminations and the system automatically performs a configuration function to assign addresses 35 + SCSI ◼ Small Computer System Interface ◼ A once common standard for connecting peripheral devices to small and medium-sized computers ◼ Has lost popularity to USB and FireWire in smaller systems ◼ High-speed versions remain popular for mass memory support on enterprise systems ◼ Physical organization is a shared bus, which can support up to 16 or 32 devices, depending on the generation of the standard ◼ The bus provides for parallel transmission rather than serial, with a bus width of 16 bits on earlier generations and 32 bits on later generations ◼ Speeds range from 5 Mbps on the original SCSI-1 specification to 160 Mbps on SCSI-3 U3 36 + Thunderbolt ◼ Provides up to 10 Gbps throughput in each direction and up to 10 Watts of power to connected peripherals ◼ Most recent and fastest peripheral connection technology to become available for general-purpose use ◼ Developed by Intel with collaboration from Apple ◼ The technology combines data, video, audio, and power into a single high-speed connection for peripherals such as hard drives, RAID arrays, video- capture boxes, and network interfaces 37 + Ethernet ◼ Predominant wired networking technology ◼ Has evolved to support data rates up to 100 Gbps and distances from a few meters to tens of km ◼ Has become essential for supporting personal computers, workstations, servers, and massive data storage devices in organizations large and small ◼ Began as an experimental bus-based 3-Mbps system ◼ Has moved from bus-based to switch-based ◼ Data rate has periodically increased by an order of magnitude ◼ There is a central switch with all of the devices connected directly to the switch ◼ Ethernet systems are currently available at speeds up to 100 Gbps 40 + Wi-Fi ◼ Is the predominant wireless Internet access technology ◼ Now connects computers, tablets, smart phones, and other electronic devices such as video cameras TVs and thermostats ◼ In the enterprise has become an essential means of enhancing worker productivity and network effectiveness ◼ Public hotspots have expanded dramatically to provide free Internet access in most public places ◼ As the technology of antennas, wireless transmission techniques, and wireless protocol design has evolved, the IEEE 802.11 committee has been able to introduce standards for new versions of Wi-Fi at higher speeds ◼ Current version is 802.11ac (2014) with a maximum data rate of 3.2 Gbps 41 + Useful Links ◼ https://www.studytonight.com/computer-architecture/input- output-organisation ◼ https://www.youtube.com/watch?v=LNPBr3WvuNg ◼ DMA: https://www.youtube.com/watch?v=wi-po2SesoE ◼ https://www.youtube.com/watch?v=54BrU82ANww 42