Instruction Set Architecture - Principles of Computer Architecture - Lecture Slides, Slides of Advanced Computer Architecture

Download Instruction Set Architecture - Principles of Computer Architecture - Lecture Slides and more Slides Advanced Computer Architecture in PDF only on Docsity! The ISA Level • The Instruction Set Architecture (ISA) is positioned between the microarchtecture level and the operating system level. – Historically, this was the only level. – It is the interface between the software and the hardware. – Programs written in high-level languages (C, C++, FORTRAN 90, etc.) are compiled into a common intermediate form - the ISA level - which the hardware executes directly. Docsity.com The ISA Level FORTRAN 90 program program FORTRAN 90 C program program compiled compiled fo ISA program to ISA program Software ISA level Renn nn nn nnn nanan nncne nanan Hardware ISA program executed by microprogram or hardware Hardware Figure 5-1. The ISA level is the interface between the com- pilers and the hardware Docsity.com The ISA Level – There are at least two modes at the ISA level: • Kernel mode is intended to run the operating system and allows all instructions to be executed. • User mode is intended to run application programs and does not permit certain sensitive instructions to be executed. – All computers divide memory up into cells that have consecutive addresses. • The most common cell size is 8 bits (called a byte). • The reason for using 8 bits is that ASCII codes are 7 bits (add one bit for parity). Docsity.com Memory Models – Bytes are grouped into 4-byte (32 bit) or 8-byte (64 bit) words with instructions available for manipulating entire words. – Many architectures require words to be aligned on their natural boundaries. • This allows more efficient memory operations. • Reading words at arbitrary addresses requires extra logic on the chip, making it bigger and more expensive. • The Pentium 4 does not require alignment in order to retain compatibility with the 8088. Docsity.com The ISA Level Address Address ——— 8 Byles —————_+ —— 8 Byes ——— 24 i i i i 24 16 IM1iwlif lis) 16 15] 14,139 ]12]11] 10] $1 8 a 15 | 14] 13112 8 | 0 a 0 Aligned 8-byte Nonaligned &-byte word at ackdirass 5 word at address 12 la} {b) Figure 3-2, An 8-byte word in a little-endian memory. (a) Aligned. (b) Not aligned. Some machines require that words in memory be aligned. Docsity.com Registers • One control register that is a hybrid kernel/user is the flags register or PSW (Program Status Word). This register contains various condition bits: – N - Set when the result was Negative – Z - Set when the result was Zero – V - Set when the result caused an oVerflow – C - Set when the result caused a Carry out of the leftmost bit – A - Set when there was a carry out of bit 3 (Auxiliary carry) – P - Set when the result had even parity Docsity.com Pentium 4 ISA Level – The Pentium 4 has three operating modes, two of which make it look like an 8088. In real mode, features added since the 8088 are turned off. • An application error causes the machine to crash. – Virtual 8086 mode makes it possible to run old 8088 programs in a protected way. • A special isolated environment that acts like an 8088 is created, except that if the program crashes, the operating system is informed. • Used when an MS-DOS window is opened. – Protected mode has four privilege levels controlled by bits in the PSW Docsity.com Pentium 4 Registers – The first four registers are general-purpose: • EAX is the main arithmetic register. • EBX is good for holding pointers • ECX plays a role in looping • EDX is needed for multiplication and division (holding half of the 64-bit products and dividends) – These registers contain 8- and 16-bit registers in the low-order bits for manipulation of 8- and 16- bit quantities, respectively. Docsity.com UltraSPARC III • The SPARC architecture is a RISC architecture based on the research done at Cal-Berkeley. • The memory structure is a linear array of 264 bytes (more than can currently be addressed). • The UltraSPARC III has two groups of registers: – 32 64-bit general-purpose registers – 32 floating-point registers Docsity.com UltraSPARC III General Registers Register | Alt. name Function RO GO Hardwired to 0. Stores into it are just ignored. R1—R7 G1-G7 | Holds global variables R8 — R13 00-05 | Holds parameters to the procedure being called R14 SP Stack pointer R15 O7 Scratch register Ri6—R23 | LO-L7 Holds local variables for the current procedure R24 -— R29 lo -15 Holds incoming parameters R30 FP Pointer to the base of the current stack frame R31 \7 Holds return address for the current procedure ® Docsity.com UltraSPARC III Register Windows – The UltraSPARC III actually has more than 32 general- purpose registers, although only 32 of them are visible to the program at a time. – This feature, known as Register Windows, is intended for the efficient support of procedure calls. – There are multiple sets of registers, which emulate the use of a stack. – The register CWP (Current Window Pointer) keeps track of which registers set is currently in use. – Register renaming is used to efficiently pass parameters. Docsity.com Pentium 4 Numeric Data Types Type 1 Bit | 8 Bits | 16 Bits | 32 Bits | 64 Bits | 128 Bits Bit Signed integer x x x Unsigned integer x x x Binary coded decimal integer x Floating point x x ® Docsity.com UltraSPARC III Data Types – The UltraSPARC III supports a wide range of data formats. • For integers it supports 8-, 16-, 32-, and 64-bit operands, both signed and unsigned. • Signed integers use two’s complement. • Floating point operands conform to the IEEE 754 standard. • BCD numbers are not supported. • All operands must be aligned in memory. • Character and string data types are not supported by special instructions. Docsity.com UltraSPARC III Numeric Data Types Type 1 Bit | 8 Bits | 16 Bits | 32 Bits | 64 Bits | 128 Bits Bit Signed integer x x x x Unsigned integer x x x x Binary coded decimal integer Floating point x x x Docsity.com Instruction Formats • An instruction consists of an opcode, usually with some additional information such as where operands come from, and where results go. • The general subject of specifying where the operands are is called addressing. • Several possible formats for level 2 instructions are shown on the next slide. Docsity.com Common Instruction Formats OPCODE OPCODE ADDRESS: (a) {b) OPCODE |ADDRESS1 | ADDRESS2 OPCODE | ADDA1 | ADDR2 | ADDRS te) (dy Figure 5-9, Four common instruction formats: (a) Zero- address instruction. (b) One-address instruction (c) Two- address instruction. (d) Three-address instruction. Docsity.com Instruction Formats • On some machines, all instructions have the same length; on others there may be many different lengths. • Instructions may be shorter than, the same length as, or longer than the word length. – Having a single instruction length is simpler and makes decoding easier, but is less efficient. Docsity.com Expanding Opcodes – The concept of a expanding opcode can best be seen through an example. – Consider a machine in which instructions are 16 bits long and addresses are 4 bits long. • This might be reasonable on a machine that has 16 registers on which all arithmetic operations take place. • One design would be a 4-bit opcode and three addresses in each instruction, giving 16 three-address instructions. Docsity.com 15 Expanding Opcodes 14 13 12 #141 #10 #9 8 7 6 5&8 4 3 2 1 e we Opeode Address 1 Address 2 Address 3 Figure 5-11. An instruction with a 4-bit opcode and three 4-bit address fields. Docsity.com Expanding Opcodes – However, if the designers need 15 three-address instructions, 14 two-address instructions, 31 one- address instructions, and 16 instructions with no address at all, they can use opcodes 0 to 14 as three-address instructions but interpret opcode 15 differently. • Opcode 15 means that the opcode is contained in bits 8 to 15 instead of 12 to 15. Docsity.com UltraSPARC III Instruction Formats Format _2 5 6 5 8 5 ta DEST | OPCODE | SRC1 |0| FP-OP SRC2 | 3 Register 1b DEST OPCODE SRC1 1 IMMEDIATE CONSTANT Immediate 2 5 3 22 2 DEST OP IMMEDIATE CONSTANT SETHI 21 4 3 22 3] |A] COND | OP PC-RELATIVE DISPLACEMENT BRANCH 2 30 4 PC-RELATIVE DISPLACEMENT CALL Figure 5-14. The original SPARC instruction formats. Docsity.com 8051 Instruction Formats Format 1 Opcode 2 Opcode Reg 3 Opcode Operand 4 Opcode 11-Bit address 5 Opcode 16-Bit address 6 Opcode Operand 1 Operand 2 Docsity.com