Download Integrated Circuit Resistors-Introduction to Microelectronic Circuits-Lecture 19 Slides-Electrical Engineering and more Slides Microelectronic Circuits in PDF only on Docsity! 1 Lecture 19, Slide 1EECS40, Fall 2003 Prof. King Lecture #19 OUTLINE • Integrated-circuit resistors • The pn Junction Diode – Depletion region & junction capacitance – I-V characteristic Reference Reading • Rabaey et al. – Chapter 3.2.1 to 3.2.2 • Howe & Sodini – Chapter 3.1-3.6 • Schwarz and Oldham – Chapter 13.2 Lecture 19, Slide 2EECS40, Fall 2003 Prof. King The resistivity ρ and thickness t are fixed for each layer in a given manufacturing process fixed designable Example: Suppose we want to design a 5 kΩ resistor using a layer of material with Rs = 200 Ω/ Integrated-Circuit Resistors = W LRR s tA circuit designer specifies the length L and width W, to achieve a desired resistance R Resistor layout (top view) Space-efficient layout 2 Lecture 19, Slide 3EECS40, Fall 2003 Prof. King The pn Junction Diode Schematic diagram p-type n-type ID + VD – Circuit symbol Physical structure: (an example) p-type Si n-type Si SiO2SiO2 metal metal ID+ VD – net donor concentration ND net acceptor concentration NA For simplicity, assume that the doping profile changes abruptly at the junction. cross-sectional area AD Lecture 19, Slide 4EECS40, Fall 2003 Prof. King • When the junction is first formed, mobile carriers diffuse across the junction (due to the concentration gradients) – Holes diffuse from the p side to the n side, leaving behind negatively charged acceptor ions – Electrons diffuse from the n side to the p side, leaving behind positively charged donor ions A region depleted of mobile carriers is formed at the junction. • The space charge due to immobile ions in the depletion region establishes an electric field which opposes carrier diffusion. Depletion Region + + + + + – – – – – p n acceptor ions donor ions 5 Lecture 19, Slide 9EECS40, Fall 2003 Prof. King Reverse Bias • As |VD| increases, the potential barrier to carrier diffusion across the junction increases*; thus, no carriers diffuse across the junction. ID (Amperes) VD (Volts) * Hence, the width of the depletion region increases. p n + + + + + – – – – – VD < 0 A very small amount of reverse current (ID < 0) does flow, due to minority carriers diffusing from the quasi-neutral regions into the depletion region and drifting across the junction. Lecture 19, Slide 10EECS40, Fall 2003 Prof. King Note that e0.6/0.026 = 1010 and e0.72/0.026 = 1012 ID is in the mA range for VD in the range 0.6 to 0.7 V, typically. I-V Characteristic 300K for Volts 026.0 == T q kT “Ideal diode” equation: )1( / −= kTqVSD DeII IS is the diode saturation current • function of ni2, AD, NA, ND, length of quasi-neutral regions • typical range of values: 10-14 to 10-17 A/µm2 ID (A) VD (V) 6 Lecture 19, Slide 11EECS40, Fall 2003 Prof. King Depletion Region Width Wj • The width of the depletion region is a function of the bias voltage, and is dependent on NA and ND: • If one side is much more heavily doped than the other (which is commonly the case), then this can be simplified: where N is the doping concentration on the more lightly doped side ( )D DA DASi j VNN NN q W − += 0 2 φε F/cm 10 12−=Siε( )DSij VqNW −≅ 0 2 φε Lecture 19, Slide 12EECS40, Fall 2003 Prof. King Junction Capacitance • The charge stored in the depletion region changes with applied voltage. This is modeled as junction capacitance j SiD j W AC ε= p n + + + + + – – – – – VD charge density (C/cm3) distance 7 Lecture 19, Slide 13EECS40, Fall 2003 Prof. King Summary: pn-Junction Diode Electrostatics • A depletion region (in which n and p are each much smaller than the net dopant concentration) is formed at the junction between p- and n-type regions – A built-in potential barrier (voltage drop) exists across the depletion region, opposing carrier diffusion (due to a concentration gradient) across the junction: • At equilibrium (VD=0), no net current flows across the junction – Width of depletion region • decreases with increasing forward bias (p-type region biased at higher potential than n-type region) • increases with increasing reverse bias (n-type region biased at higher potential than p-type region) – Charge stored in depletion region capacitance ( )DSij VqNW −≅ 0 2 φε j SiD j W AC ε= = 20 ln i DA n NN q kTφ Lecture 19, Slide 14EECS40, Fall 2003 Prof. King Summary: pn-Junction Diode I-V • Under forward bias, the potential barrier is reduced, so that carriers flow (by diffusion) across the junction – Current increases exponentially with increasing forward bias – The carriers become minority carriers once they cross the junction; as they diffuse in the quasi-neutral regions, they recombine with majority carriers (supplied by the metal contacts) “injection” of minority carriers • Under reverse bias, the potential barrier is increased, so that negligible carriers flow across the junction – If a minority carrier enters the depletion region (by thermal generation or diffusion from the quasi-neutral regions), it will be swept across the junction by the built-in electric field “collection” of minority carriers reverse current ID (A) VD (V)