ECEN 4517/5517 Lecture 4: Step-up DC-DC Converter with Isolation and Feedback Controller, Study notes of Electrical and Electronics Engineering

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ECEN 4517 1 Lecture 4 ECEN 4517/5517 Step-up dc-dc converter with isolation (flyback) Feedback controller to regulate HVDC Experiment 3 weeks 2 and 3: interleaved flyback and feedback loop Parallel two flybacks with phase-shifted gate drive signals 12 VDC HVDC: 120 - 200 VDC AC load 120 Vrms 60 Hz Battery DC-AC inverter H-bridge DC-DC converter Isolated flyback +– d(t) Feedback controller Vref Digital controller d(t) + vac(t) – ECEN 4517 2 Due dates and goals Right now: Prelab assignment for Exp. 4 Part 1 (one from every student) Due within five minutes of beginning of lecture This week in lab (Feb. 3-5): Final reports for Exps. 1 and 2 due Begin Exp. 3: construct and debug basic flyback power stage Next week in lab (Feb. 10-13): Get parallel flyback power stages working at 85 W Begin simulation of ac transfer functions and feedback loop design ECEN 4517 4 Effect of transformer leakage inductance + – LM + v – Vg Q1 D11:n C Transformer model iig R Ll + vl – + vT(t) – • Leakage inductance Ll is caused by imperfect coupling of primary and secondary windings • Leakage inductance is effectively in series with transistor Q1 • When MOSFET switches off, it interrupts the current in Ll • Ll induces a voltage spike across Q1 t Vg + v/n vT(t) iRon DTs {Voltage spikecaused byleakageinductance If the peak magnitude of the voltage spike exceeds the voltage rating of the MOSFET, then the MOSFET will fail. ECEN 4517 5 Protection of Q1 using a voltage-clamp snubber + – + v – Vg Q1 D11:n C Flyback transformer ig R + vT(t) – CsRs – vs + Snubber{ • Snubber provides a place for current in leakage inductance to flow after Q1 has turned off • Peak transistor voltage is clamped to Vg + vs • vs > V/n • Energy stored in leakage inductance (plus more) is transferred to capacitor Cs, then dissipated in RsUsually, Cs is large Decreasing Rs decreases the peak transistor voltage but increases the snubber power loss See supplementary flyback notes for an example of estimating Cs and Rs ECEN 4517 6 Overvoltage on output diode + – LM + v – Vg Q1 D11:n C Transformer model iig R Ll1 + vl – + vT(t) – Ll2Diode turn-off (reverse recovery) transition: Transformer leakage inductance causes voltage ringing and overshoot on secondary diode Leakage inductance plus diode output capacitance form resonant circuit: tArea – Qr t t3t1 t2 vB(t) iL(t) –V2 0 0 + – LiL(t) vL(t) + – + – Silicon diodevi(t) CvB(t) iB(t) diode capacitance leakage inductance secondary induced voltage ECEN 4517 9 Increasing the output power Week 2 circuit Interleaving of parallel-connected flyback converters: • AC components of phase-shifted input current waveforms partially cancel out • Less rms capacitor current per unit of output power Produce 85 W output power by end of week 2 ECEN 4517 10 Exp. 3 Part 3 Regulation of output voltage via feedback snubber PWM Compensator +– Vref Vbatt vHVDC • Model and measure control-to-output transfer function Gvd(s) • Design and build feedback loop • Measure loop gain to verify phase margin and crossover frequency • Demonstrate closed-loop regulation of vHVDC ECEN 4517 11 Negative feedback: a switching regulator system + – + v – vg Switching converterPower input Load –+ Compensator vref Reference input HvPulse-width modulator vc Transistor gate driver Gc(s) H(s) ve Error signal Sensor gain iload ECEN 4517 14 The loop gain T(s) + – + v – vg Switching converterPower input Load –+ Compensator vref Reference input HvPulse-width modulator vc Transistor gate driver Gc(s) H(s) ve Error signal Sensor gain iload Loop gain T(s) = product of gains around the feedback loop More loop gain ||T|| leads to better regulation of output voltage T(s) = Gvd(s) H(s) Gc(s) / VM Gvd(s) = power stage control-to-output transfer function PWM gain = 1/VM. VM = pk-pk amplitude of PWM sawtooth ECEN 4517 15 Phase Margin A test on T(s), to determine stability of the feedback loop The crossover frequency fc is defined as the frequency where || T(j2 fc) || = 1, or 0 dB The phase margin m is determined from the phase of T(s) at fc , as follows: m = 180˚ + (T(j2 fc)) If there is exactly one crossover frequency, and if T(s) contains no RHP poles, then the quantities T(s)/(1+T(s)) and 1/(1+T(s)) contain no RHP poles whenever the phase margin m is positive. ECEN 4517 16 Example: a loop gain leading to a stable closed-loop system (T(j2 fc)) = – 112˚ m = 180˚ – 112˚ = + 68˚ fc Crossover frequency 0 dB –20 dB –40 dB 20 dB 40 dB 60 dB f fp1 fz T 0˚ –90˚ –180˚ –270˚ m T T T 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz Fundamentals of Power Electronics Chapter 8: Converter Transfer Functions94 8.4. Measurement of ac transfer functions and impedances Network Analyzer Injection source Measured inputs vy magnitude vz frequency vz output vz + – input vx input + – + – vy vx vy vx Data 17.3 dB – 134.7˚ Data bus to computer Fundamentals of Power Electronics Chapter 8: Converter Transfer Functions95 Swept sinusoidal measurements • Injection source produces sinusoid of controllable amplitude and frequency • Signal inputs and perform function of narrowband tracking voltmeter: Component of input at injection source frequency is measured Narrowband function is essential: switching harmonics and other noise components are removed • Network analyzer measures vz vx vy ∠vy vx vy vx and Fundamentals of Power Electronics Chapter 8: Converter Transfer Functions96 Measurement of an ac transfer function Network Analyzer Injection source Measured inputs vy magnitude vz frequency vz output vz + – input vx input + – + – vy vx vy vx Data –4.7 dB – 162.8˚ Data bus to computer Device under test G(s) in pu t output VCC DC bias adjust DC blocking capacitor • Potentiometer establishes correct quiescent operating point • Injection sinusoid coupled to device input via dc blocking capacitor • Actual device input and output voltages are measured as and • Dynamics of blocking capacitor are irrelevant vx vy vy(s) vx(s) = G(s)