Introduction to Network Processors: Understanding the Role and Architecture of NP Systems, Slides of Computer Architecture and Organization

Download Introduction to Network Processors: Understanding the Role and Architecture of NP Systems and more Slides Computer Architecture and Organization in PDF only on Docsity! Lecture 1: Introduction to Network Processors Docsity.com Outlin e • Introduction to NP Systems • Relevant Applications • Design Issues and Challenges • Relevant Software and Benchmarks • A case study: Intel IXP network processors Docsity.com Typical NP Architecture SDRAM (Packet buffer) SRAM (Routing table) multi-threaded processing elements Co-processor Input ports Output ports Network Processor Bus Bus Docsity.com TCP/IP Model • ISO OSI (Open Systems Interconnection) not fully implemented • Presentation and Session layers not present in TCP/IP Application Pre. Session Transport Network Data Link Physical 7 6 5 4 3 2 1 Application TCP IP Host-to-Net OSI TCP/IP Docsity.com Processing Tasks Policy Applications Network Management Signaling Topology Management Queuing / Scheduling Data Transformation Classification Data Parsing Media Access Control Physical Layer Data Plane Control Plane Source: Network Processor Tutorial in Micro 34 - Mangione-Smith & Memik Docsity.com Applications: IPv4 Routing • Routers determine next hop and forward packets Router A B C P P P Docsity.com URL-based switching – My NSF Project • Increase efficiency • Tasks – Traverse the packet data (request) for each arriving packet and classify it: • Contains ‘.jpg’ -> to image server • Contains ‘cgi-bin/’ -> to application server Switch Image Server Application Server HTML Server www.yahoo.com Internet GET /cgi-bin/form HTTP/1.1 Host: www.yahoo.com… APP. DATA TCP IP Docsity.com Organizing Processor Resources • Design decisions: – High-level organization – ISA and micro architecture – Memory and I/O integration • Today’s commercial NPs: – Chip multiprocessors – Most are multithreaded – Exploit little ILP (Cisco does) – No cache – Micro-programmed Docsity.com Architectural Comparisons (cont.) Tim e ( pr oc es so r c yc le) Superscalar Fine-Grained Coarse-Grained Multiprocessing Thread 1 Thread 2 Thread 3 Thread 4 Thread 5 Idle slot Simultaneous Multithreading Docsity.com Tasks and Services Three Benchmarks used in the experiment Docsity.com Some Challenges • Intelligent Design – Given a selection of programs, a target network link speed, the ‘best’ design for the processor • Least area • Least power • Most performance • Write efficient multithreaded programs – NPs have • Heterogeneous computer resources • Non-uniform memory • Multiple interacting threads of execution • Real-time constraints – Make use of resources • How to use special instructions and hardware assists – Compilers – Hand-coded – Multithreaded programs • Manage access to shared state • Synchronization between threads Docsity.com IXP1200 Microengine • 4 hardware contexts – Single issue processor – Explicit optional context switch on SRAM access • Registers – All are single ported – Separate GPR – 256*6 = 1536 registers total • 32-bit ALU – Can access GPR or XFER registers • Shared hash unit – 1/2/3 values – 48b/64b – For IP routing hashing • Standard 5 stage pipeline • 4KB SRAM instruction store – not a cache! • Barrel shifter Docsity.com IXP 2400 Block Diagram • XScale core replaces StrongARM • Microengines – Faster – More: 2 clusters of 4 microengines each • Local memory • Next neighbor routes added between microengines • Hardware to accelerate CRC operations and Random number generation • 16 entry CAM ME0 ME1 ME2 ME3 ME4 ME5 ME6 ME7 Scratch /Hash /CSR MSF Unit DDR DRAM controller XScale Core QDR SRAM controller PCI Docsity.com Different Types of Memory Type Width (byte) Size (bytes) Approx unloaded latency (cycles) Notes Local 4 2560 1 Indexed addressing post incr/decr On-chip Scratch 4 16K 60 Atomic ops SRAM 4 256M 150 Atomic ops DRAM 8 2G 300 Direct path to/fro MSF Docsity.com IBM PowerNP • 16 pico-procesors and 1 powerPC • Each pico-processor – Support 2 hardware threads – 3 stage pipeline : fetch/decode/execute • Dyadic Processing Unit – Two pico-processors – 2KB Shared memory – Tree search engine • Focus is layers 2-4 • PowerPC 405 for control plane operations – 16K I and D caches • Target is OC-48 Docsity.com Motorola C-Port C-5 Chip Architecture text text Queue Mngt Unit Fabric Processor Table Lookup Unit Buffer Mngt Unit Executive Processor CP-0 PHY CP-1 PHY CP-2 PHY CP-3 PHY Cluster text CP- 12 PHY CP- 13 PHY CP- 14 PHY CP- 15 PHY Cluster 60Gbps Busses SRAMSRAM SRAMSwitchFabric P R O M P C I C O N TR O L Docsity.com