Download Introduction to CMOS Design - Lecture Notes | ECE 464 and more Study notes Microelectronic Circuits in PDF only on Docsity! 1© 2006, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes Introduction to CMOS Design Dr. Paul D. Franzon Outline 1. CMOS Transistors 2. CMOS cell design 3. Transistor Sizing References Smith and Franzon, Chapter 11 Weste and Eshraghian, Principles of CMOS VLSI Design, A Systems Perspective 2© 2006, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes CMOS Transistors 1. nMOS Transistor n n p substrate Polysilicon Conductor Silicon Oxide Gate Gate Source Drain Drain Drain SourceSource GateGate substrate L W 5© 2006, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes ... nMOS Transistor Theory .... Transistor States 3. Saturatation Region Ids = Β (Vgs - Vt)2 when 0 < Vgs - Vt < Vds Q: Draw a large signal equivalent model for transistor in Linear and Saturation States for falling output: Transistor Characteristics: t=0 Vo<VDD-Vtn 6© 2006, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes Transistor Characteristics 7© 2006, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes CMOS Inverter Static CMOS Inverter: What are the transistor states when: Vin = 0 V Vin = 5 V given |Vt| = 1 V VoutVin 5V 0 V n1 p1 n1 : VGS < Vt : Off p1 : |VGS| > |Vt|, Vds=0 : Linear n1 : VGS > Vt, VDS=0 : Linear p1 : |VGS| < |Vt| : Off 10© 2006, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes DFF Clock buffer (guarantees clock edge rate and thus tsu, thold) Master Slave 11© 2006, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes DFF D Ck’ Ck Function: D Ck : Output 0 0 : 0 1 : 1 0 : 1 1 : 1 z 0 0 12© 2006, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html ECE 464/520 Class Notes DFF Function: Regenerative Latch - Feedbacks MQ when Ck high
