Download Introduction to Computer Architecture II - Study Guide | CS 270 and more Study notes Computer Architecture and Organization in PDF only on Docsity! Example: A computer has a CPU with a 1.0 ns cycle time and a two level cache. The first level cache is a 64 KB, 4- way associative with a block size of 32 bytes. The second level cache is a 1 MB, direct mapped with a block size of 256 bytes. A hit in the first level cache results in moving the item requested to the CPU in one CPU cycle. A miss in the first level cache causes an access to the second level cache which has a 4.0 ns access time and a transfer rate of 16 bytes per 1.0 ns. A miss in the second level cache causes an access to the main memory which has a 40.0 ns access time and a transfer rate of 32 bytes per 2.0 ns. We will assume that the data is always in the memory. The miss rate of the first level cache is 0.0089. The local miss rate of the second level cache is 0.220. (a) Compute the average memory access time in ns and in CPU cycles. (b) What fraction (in %) of the average access time is due to (i) second level cache misses and (ii) first level cache misses? 7.25 [10] <§7.3> Using the series of references given in Exercise 7.9, show and misses and final cache contents for a two-way set-associative cache one word blocks and a total size of 16 words. Assume LRU replacement. Same for 4-way, 8-way and fully associative. In More Depth: Average Memory Access Time To capture the fact that the time to access data for both hits and misses affects performance, designers often use average memory access time (AMAT) as a way to examine alternative cache designs. Average memory access time is the average time to access memory considering both hits and misses and the frequency of different accesses; it is equal to the following: AMAT = Hit time + (MR x MP) AMAT is useful as a figure of merit for different cache systems. 7.17 [5] <§7.2> Find the AMAT for a processor with a 2 ns clock, a miss penalty of 20 clock cycles, a miss rate of 0.05 misses per access, and a cache access time (including hit detection) of 1 clock cycle. Assume that the read and write miss penalties are the same and ignore other write stalls.
