Introduction to Digital Integrated Circuits - Problems with Solutions | EL ENG 141, Assignments of Electrical and Electronics Engineering

Download Introduction to Digital Integrated Circuits - Problems with Solutions | EL ENG 141 and more Assignments Electrical and Electronics Engineering in PDF only on Docsity! 1 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on November 5, 2004 by Henry Jen and Stanley Wang (henryjen@eecs) Borivoje Nikolic Homework #8:Logical Effort and Dynamic Logic EECS 141 Problem #1 Logical Effort of Transmission Gates out 0.0V 2.5V 2.5V in CL Wp/Lmin Wp/Lmin Wn/Lmin Wn/Lmin Figure 1 Calculate the logical effort of the circuit shown in Figure 1 given that Wp=2Wn=2Wmin. If eqpR and eqnR the PMOS and NMOS equivalent resistances respectively, the equivalent resistance of the circuit during pull-up and pull-down is respectively )//( eqneqpeqpeqLH RRRR += )//( eqneqpeqneqHL RRRR += Since RRR eqneqp == the above equations give 2/3RRRR eqHLeqLHeq === For the equivalent resistance to be equal to that of the minimum sized inverter (R), the input transistors should be made 3/2 times larger, increasing thus the input capacitance by 3/2 (compared to the minimum sized inverter). Hence, the logical effort of the circuit is 2/3=g 2 Problem #2 Domino logic Suppose we want to implement two logic functions given by F=A+B+C and G=A+B+C+D. Assume both true and complementary signals are available. a) Implement these functions in dynamic CMOS as cascaded φ stages so as to minimize the total transistor count. VDD VDD G A B C φ φ D φ φ F DCBADFG +++== . b) Discuss any conditions under which this implementation would fail to operate properly. When A+B+C=1, F will make a transition 1->0, which cannot be applied directly to the second stage. If D=0 for example, G will be discharged at the beginning of the evaluation phase. Therefore G will have an incorrect value (0) for this combination of input signals. c) Design an np-CMOS implementation of the same logic functions. Does this design display any of the difficulties of part b)?