Download VHDL Laboratory: Understanding VHDL Syntax and Components and more Lab Reports Computer Architecture and Organization in PDF only on Docsity! CSCE 230L Laboratory 91 Section: ______________________________ Date: _____________________ Name: ________________________________ CSE Login ID:_______________ Logic Design with VHDL Objectives 1. Learn the basic syntax and semantics of the VHSIC Hardware Description Language (VHDL). 2. Gain experience in specifying behavioral and structural VHDL descriptions of hardware components Introduction The Very High-Speed Integrated Circuit (VHSIC) program was a government sponsored program created to usher in a new generation of high-speed integrated circuits. One product of this program was the VHSIC Hardware Description Language (VHDL). VHDL includes facilities for describing logical structure and function of digital systems at a number of levels of abstraction, from system level down to the gate level. In addition to providing a means of expressing hardware specification, it may also be directly translate some specifications into hardware. Prelab Reading Assignment: Read pages 3-6, 43-52 in the VHDL Tutorial on the textbook CD (Select the “Tutorials” button from the menu and click “VHDL Tutorial”). Look at the circuit “reg4” described in figures 2-1, 2-2, and 2-3 of the VHDL Tutorial. 1. What does this circuit do? What is its purpose? 1 Portions of this document were taken from Introductory VHDL: From Simulation to Synthesis by Sudhakar Yalamanchili and VHDL Tutorial by Peter J. Ashenden. UNL-CSE CSCE 230L Lab #8 Page 1 of 4 2. What is the difference between the “entity” statement shown in figure 2-2 and the “architecture” statement shown in figure 2-3? 3. What is the purpose of the “en” and “clk” inputs? What would happen if the “en” input were removed (assume the statements enclosed in the “if en=1” statement were executed unconditionally)? A process is an encapsulation mechanism for VHDL similar to functions or procedures in standard programming languages. A process statement may be placed inside an architecture statement. For the syntax, see page 50 of the tutorial. The process in the architecture body includes the input ports in the sensitivity list after the keyword process. This is a list of signals to which the process is sensitive. When any of these signals changes value, the process resumes and executes the sequential statements. After it has executed the last statement, the process suspends again. 4. Both “clr” and “clk” are in the sensitivity list for the state_change process of the D- flip-flop shown in figure 4-2. Why are both “clk” and “clr” in the sensitivity list? What would happen if either was missing? What would happen if “D” were added to the list? UNL-CSE CSCE 230L Lab #8 Page 2 of 4
