VHDL Reference Sheet: Entities, Ports, Signals, and Processes - Prof. Kevin Bolding, Study notes of Electrical and Electronics Engineering

Download VHDL Reference Sheet: Entities, Ports, Signals, and Processes - Prof. Kevin Bolding and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! VHDL Reference Sheet LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; ENTITY __entity_name IS PORT( __input_name, __input_name: IN STD_LOGIC; __input_vector_name: IN STD_LOGIC_VECTOR(__high downto __low); __output_name, __output_name: OUT STD_LOGIC; __output_vector_name: OUT STD_LOGIC_VECTOR(__high downto __low); __buffer_name, __buffer_name: BUFFER STD_LOGIC); END __entity_name; ARCHITECTURE a OF __entity_name IS SIGNAL __signal_name : STD_LOGIC; SIGNAL __signal_name : STD_LOGIC_VECTOR (__high downto __low); BEGIN -- Architecture Body --- END a; CASE __expression IS WHEN __constant_value => __statement; __statement; WHEN __constant_value => __statement; __statement; WHEN OTHERS => __statement; __statement; END CASE; IF __expression THEN __statement; __statement; ELSIF __expression THEN __statement; __statement; ELSE __statement; __statement; END IF; TYPE __enumerated_type_name IS (__name, __name, __name); SIGNAL __signal_name : __type_name; PROCESS (__signal_name, __signal_name, __signal_name) BEGIN -- Process Body -- END PROCESS;