Introduction to Power Electronics Circuit: Topologies | ECE 562, Study notes of Electrical and Electronics Engineering

Download Introduction to Power Electronics Circuit: Topologies | ECE 562 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! 1 LECTURE 4 Introduction to Power Electronics Circuit Topologies: The Big Three I. POWER ELECTRONICS CIRCUIT TOPOLOGIES A. OVERVIEW B. BUCK TOPOLOGY C. BOOST CIRCUIT D. BUCK - BOOST TOPOLOGY E. COMPARISION OF THE BIG THREE II. TOPOLOGY OF L-C OUTPUT FILTERS A. C ALWAYS Located ACROSS Vout B. L LOCATED BETWEEN CRUDE UNFILTERED Vdc AND STABILIZED Vout 1. BUCK 2. BOOST 3. BUCK-BOOST 4. LOW RIPPLE APPROXIMATION FOR OUTPUT SIGNALS AT fsw a) INDUCTOR RIPPLE: ∆i V L dt switch= ( ) b) CAPACITOR RIPPLE: ∆V I C dt switch= ( ) dt(switch)=(Duty cycle)*Ts(period of fsw) 2 Introduction to Power Electronics Circuit Topologies: The Big Three A. OVERVIEW The Inductor in any PWM converter plays the role of a mechanical flywheel in that it stores energy between pulses. The solid state switches pulse energy at the switching frequency into the PWM circuit from the input but the inductor stores energy so that the energy drawn to the load does not appear pulsed at all. We will see below that both the precise location of the inductor in the circuit topology as well as the physical location of the switch on the specific terminal of the inductor are crucial to realize the three major PWM circuit topologies. The inductor –switch combination will have three unique topological locations. In section B, for simplicity, we will use the three major topologies to convert a DC input to various DC outputs that are both below and above the original V(in) in voltage. We will express the steady state transfer function of all converters as a function of the duty cycle: F(D) B. BUCK TOPOLOGY (a) BUCK TOPOLOGY: Inductor attached to c in series. note how l avoids kvl violations for brief periods by acting as a buffer between vin and vout as well as storing energy. D C fs D/D' 5 For now realize that the boost circuit while delivering an output voltage above V(in) does have to ask the solid state switch to handle a peak current 6 times the nominal average current when the switch is on. When the switch is off the solid state switch must withstand across itself a voltage up to the full output value. 6 C. BUCK-BOOST TOPOLOGY: Inductor is connected in parallel with C which acts as a polarity reverser. Given +vdc as input in we generate -vdc out for a switch duty cycle of ½. Many analog circuits require both + and - vdc supplies and this is an easy way to do it. VDC VOUT the inductor l again avoids kvl violations by acting as a current source temporarily. •Vout(MINIMUM) IS NOW ZERO •Vout IS OPPOSITE POLARITY TO vdc due to current direction in the inductor that charges the c. • V L dt idc L=∫ ∆ ⇒ iL DOES NOT CHANGE instantaneously so the capacitor charges negatively. •FOR BUCK-BOOST EITHER |Vout| > Vdc OR |Vout| < Vdc IS POSSIBLE •Vout / Vin = -D / (1-D). non-linear dependence on d will be shown in lectures 5-7 On the following page we show schematically the waveforms for the buck/boost circuit for both the switch on and the switch off. Again the ability to generate voltages above the input voltage comes at the price of expensive solid state switches. With the switch on we need to pass nearly 6 times the average current. With the switch off we need to stand off across the switch V(in) + V(out). 7 In preparation for your midterm exam, look at the attached schematic on pg. 8 of a flyback converter slowly - don’t panic. try to find only the essential power electronics portions. (1) identify the crude dc generation in the upper left driven by 120 ac mains. this CRUDE DC IS DRIVEN BY THE SWITCH #1 INTO THE TRANSFORMER PRIMARY. (2) On the right side of the schematic notice the three secondaries of the transformers with the three dc outputs: 5, 12, and 30 v. (3) Find the cmos transistor Q1 (middle) which is the switching transistor. From the gate of this cmos switch the gate control circuitry may also be found. We will spend the rest of the semester detailing how such circuits work. 10 From the above approach we need to pick a starting point. We will focus next of the output filter design in the remainder of this lecture and in lectures 5 and 6. E. BASIC TOPOLOGIES OF PASSIVE L-C FILTERS We will use L-C filters both to remove vac signals lost to conversion and to avoid kvl and kil law violations from the switching. 1. DC OUTPUT REACTIVE FILTER (L-C). This places a series L between two voltages sources vin and vout. It also removes or reduces the switch signal at fs and passes only dc if designed properly. lets look at the two 11 pieces of an L-C filter seperately for clarity of each role. first the ouput capacitor. a. FIXED CAPACITOR LOCATION: C ALWAYS PARALLELS RL RAW SIGNAL V(fSW)+V(DC) VoutC RL •C is in parallel with vout •∆vout/vout is the quantitative regulation desired, ic = c*dvc/dt •∆V I C dtcap out= ∫ ⇒ Vc DOESN’T CHANGE INSTANEOUSLY. It takes time to do so. The time scale of interest is some function of tsw. ∆v ∼ i/c dt which implies for fixed i, ∆v is smaller for large CAPACITOR values. for crude estimates of the desired C values, use the linear approximation. If given or specified the ∆v value allowed, iout required, and dt from fs, we can determine proper “C” in a quick calculation. b. VALUE OF L DESIRED •INDUCTOR IS OFTEN IN SERIES WITH Vdc AND Vout FOR A BUCK CIRCUIT Vdc Vout VL=LdiL/dt V V L dt idc out L − =∫ ∆ 12 It is a fraction of ts - ∆ts or d’ts given vdc - vout (fixed) and dt (switch) for a specified ∆il variation we fix l.Over a cycle of fsw the ∆il/iout can be specified. We can then fix the required “l”. Higher fs and smaller dt allows for smaller “L”. For compact and light power supplies small L is a desired goal. C. CONSIDER δ FUNCTION CURRENT CHARGING OF A CAPACITOR, C, TO VO AT fsw The vout will display RC decay in between δ function charging due to load dc current Vout 1/fs t If this δ function charging occurs via a wire with stray inductances which are typically 5nf/cm at high frequencies, then the switching waveform would then appear as a decaying sinusoid with both overshoot and undershoot at a frequency w = 1 LC and decay envelope with τ = RC Vout 1/fs t