Inverter Related - Microelectronic Devices and Circuits - Exam, Exams of Analysis and Design of Digital Integrated Circuits

Download Inverter Related - Microelectronic Devices and Circuits - Exam and more Exams Analysis and Design of Digital Integrated Circuits in PDF only on Docsity! fa-2 Microelectronic Devices and Circuits- EECS105 Second Midterm Exam Friday, November 20, 1998 Costas J. Spanos University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences Your Name: _________________________________________________ (last) (first) Your Signature: ______________________________________________ 1. Print and sign your name on this page before you start. 2. You are allowed two, 8.5"x11" handwritten sheets with formulas. No books or notes! file:///C|/Documents%20and%20Settings/Jason%20Raft...20105%20-%20Fall%201998%20-%20Spanos%20-%20MT2.htm (1 of 8)1/27/2007 4:43:28 PM fa-2 3. Do everything on this exam, and make your methods as clear as possible. Problem 1 ______/30 Problem 2 ______/35 Problem 3 ______/35 TOTAL ______/100 Problem 1 of 3 Answer each question briefly and clearly. (30 points) How is the voltage gain of a CMOS inverter related to the transconductances of its transistors? (5 pts) Why are CMOS NAND gates preferable to CMOS NOR gates? (5 pts) Why do you need an n-channel and a p-channel transistor in parallel in order to have a proper "pass" file:///C|/Documents%20and%20Settings/Jason%20Raft...20105%20-%20Fall%201998%20-%20Spanos%20-%20MT2.htm (2 of 8)1/27/2007 4:43:28 PM fa-2 c) Sketch and label the voltage transfer characteristic with VIL, VIH, VOL, VOH, VM. (7 pts) d) What are the values of NML and NMH? (7 pts) e) Would noise margins improve if you made the devices longer, while keeping everything else fixed? (Give a yes/no answer and explain it in brief qualitative terms) (7 pts) file:///C|/Documents%20and%20Settings/Jason%20Raft...20105%20-%20Fall%201998%20-%20Spanos%20-%20MT2.htm (5 of 8)1/27/2007 4:43:28 PM fa-2 Problem 3 of 3 (35 points) A CMOS cascade transconductance amplifier and the device data are shown above. There is no backgate effect. For each of the following questions, make sure that you show the expression before you plug in the specific values. A correct expression is worth 70% of the credit, even if the numerical calculation is incorrect! (a) Find the (W/L)1 for M1, so that the small signal transconductance iout/vs = 1mS. Assume RL = 0Ω (short circuit output current) for this part. (7 pts) file:///C|/Documents%20and%20Settings/Jason%20Raft...20105%20-%20Fall%201998%20-%20Spanos%20-%20MT2.htm (6 of 8)1/27/2007 4:43:28 PM fa-2 (b) Calculate the value of VBIAS using the (W/L)1 calculated in part (a) such that IOUT = 0A. (7 pts) (c) Calculate the output resistance of this transconductance amplifier. (7 pts) (d) What is the maximum value of the load resistor RL at which the overall transconductance is degraded by 20% from the original value of 1mS? (7 pts) file:///C|/Documents%20and%20Settings/Jason%20Raft...20105%20-%20Fall%201998%20-%20Spanos%20-%20MT2.htm (7 of 8)1/27/2007 4:43:28 PM