Junction Field-Effect Transistors or JFETS - Lecture Slides | ECE 4430, Study notes of Electrical and Electronics Engineering

Download Junction Field-Effect Transistors or JFETS - Lecture Slides | ECE 4430 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! JFETs (5/11/00) Page 1 ECE 4430 - Analog Integrated Circuits and Systems  P.E. Allen, 2000 1.5 - JUNCTION FIELD-EFFECT TRANSISTORS (JFETS) INTRODUCTION Objective The objective of this presentation is: 1.) Characterize the behavior of the junction field-effect transistor (JFET) 2.) Develop the large and small signal models of the JFET Outline • Operation of the JFET • Large signal model of the JFET • Small signal model of the JFET JFETs (5/11/00) Page 2 ECE 4430 - Analog Integrated Circuits and Systems  P.E. Allen, 2000 OPERATION OF THE JFET General Introduction The junction field-effect transistor uses a reverse biased pn junction to vary the cross-section of a channel through which current flows. The control (input) voltage is the reverse bias voltage which determines the amount of current flowing from the drain to source. Schematic: Fig.1.5-1 + - vDS D G S vGS iD + - + - vDS D G S vGS iD + - iG iG p-channel n-channel JFETs (5/11/00) Page 5 ECE 4430 - Analog Integrated Circuits and Systems  P.E. Allen, 2000 Derivation of the JFET Large Signal Model Based on the previous slide. 1.) Ohm’s law for conduction in the channel: Jy = σΕy ⇒ -iD Wb(y) = -σ dV(y) dy where W = width of the channel perpendicular to the plane of the previous view. 2.) Since iD is constant in the channel, integration of the above gives, iD ⌡⌠ 0 L dy = σW ⌡⌠ 0 v(L) b(y)dv where v(L) is the voltage at a distance of L from the source designated also as v’DS. 3.) Substituting b(y) into the above and performing the integration gives, iD = Go       v’DS + 2 3 K 1 a (ψ o + vGS - v’DS) 3/2 - 2 3 K 1 a (ψ o + vGS ) 3 /2 where Go = 2aσW L 4.) The quantity a can be determined by noting that the depletion layer width, X(y), equals half the channel depth when vR(y) = Vp where Vp is the pinch-off voltage. ∴ a = X(y) = K1 ψo+Vp 5.) Substituting into the above gives, iD = Go       v’DS + 2 3 (ψ o + vGS - v’DS)3/2 - (ψ o + vGS )3 /2 (ψ o + V p )1 /2 JFETs (5/11/00) Page 6 ECE 4430 - Analog Integrated Circuits and Systems  P.E. Allen, 2000 Output Characteristics of the p -channel JFET Channel not yet pinched off: Fig.1.5-4 iD v'DS -Vp 3 4 Vp- -(Vp-Vx) VGS=0 VGS= 14 Vp VGS=Vx IDSS Pinch-off occurs when vGS - v’DS = Vp (It is found by differentiating iD with respect to v’DS and setting it equal to zero.) If IDSS is defined as the value of iD when vGS = 0, (v’DS = Vp) we may write the previous expression as, IDSS = Go       V p + 2 3 (ψo - v’DS)3/2 - (ψo)3/2 (ψ o + V p )1 /2 JFETs (5/11/00) Page 7 ECE 4430 - Analog Integrated Circuits and Systems  P.E. Allen, 2000 JFET in Pinch-Off n+ emitter iD VDS Vp n collector L v(y) X(y) b(y)2a y L0Fig. 1.5-5 X(y) Channel Pinched-off A Note: The current does not stop flowing when the channel is pinched off. It does however stop increasing with increasing vDS and becomes flat as shown below. Fig.1.5-6 iD v'DS -Vp 3 4 Vp- -(Vp-Vx) VGS=0 VGS= 14 Vp VGS=Vx IDSS JFETs (5/11/00) Page 10 ECE 4430 - Analog Integrated Circuits and Systems  P.E. Allen, 2000 Summary of the JFET Large Signal Model Large signal model: IDSS(1 - vGS Vp ) 2 + - vGS G D S S Fig. 1.5-9 Signs for the JFET variables: Type of JFET Vp IDSS vGS p-channel Positive Negative Normally positive n-channel Negative Positive Normally negative JFETs (5/11/00) Page 11 ECE 4430 - Analog Integrated Circuits and Systems  P.E. Allen, 2000 JFET Breakdown Voltage Output characteristics: Fig.1.5-10 -1-2-3-4-5-6-7 -1mA -2mA iD vDS BVDGO VGS = 1.0V VGS = 0.5V VGS = 0V Note that, BVDG = BVDGO - VGS JFETs (5/11/00) Page 12 ECE 4430 - Analog Integrated Circuits and Systems  P.E. Allen, 2000 JFET SMALL SIGNAL MODEL Frequency Independent Small Signal Model Schematic: Fig.1.5-11 gmvgs rovgs + - vds + - idD G S D G S Parameters: gm = diD dvGS |Q = - 2IDSS Vp       1+ VGS Vp = gm0       1+ VGS Vp where gm0 = - 2IDSS Vp ro = diD dvDS |Q = λIDSS      1+ VGS Vp 2 ≈ 1λID Typical values of IDSS and Vp for a p-channel JFET are -1mA and 2V, respectively. With λ = 0.02V-1 and ID = 1mA we get gm = 1mA/V or 1mS and ro = 50kΩ.