Kirchhoff's Laws and Circuit Analysis, Exams of Physics

Download Kirchhoff's Laws and Circuit Analysis and more Exams Physics in PDF only on Docsity! Electronic 1: Lecture 24 • Course Review • Final Exam (comprehensive) Kirchhoff’s Laws Kirchhoff’s Voltage Law (KVL): Loop Vi = 0 Kirchhoff’s Current Law (KCL): Node Ii = 0 Watch your (implicit) sign conventions !!! All the rest: Ohm’s law: 2 + 4 = 6, 1/3 + 1/6 = , 2 + 9 = 11 (What? !) V1 V2 R1 R2 R3 Mesh AnalysisPlanar circuits: all crossing lines are connected! i1 i2 determine mesh currents: assign currents to all meshes use KVL on each mesh solve the resulting equations… Let Ii be the current through Ri mesh 1 i1 voltages: -V1 + R1i1 + R3(i1-i2) = 0 mesh 2 i2 voltages: R2i2 + V2 + R3(i2-i1) = 0 2 equations, 2 unknowns solved! X X v v1 v2 Superposition 6V 3A 8 4 6V 3A 8 4 6V 3A 8 4 Voltage or current is algebraic sum of the voltages and currents by individual voltage and current sources: 1. turn off all independent sources save one 2. repeat for all independent sources 3. add the contributions Q: voltage across the 4 resistor: v = v1+v2 • mesh analysis: 12 i1 – 6V = 0 i1 = 0.5A 2. node analysis (ground at bottom!): i2 = 3A (1 – 8 /(4 +8 )) i2 = 2A 3. Sum it: v = 4 i1 + 4 i2 = 2V + 8V = 10V Thevenin (Norton) Equivalent Leon-Charles Thevenin (1857-1927, France) Any linear two terminal circuit can be replaced by a … RTeq UTeq … voltage source in series with a Resistor (1883) or a … (also: Hermann von Helmholtz, 1853) Edward Lawry Norton (1898-1983, USA) INeq RNeq … current source in parallel with a resistor (Nov. 1926). (also: Hans Ferdinand Mayer, 1926) Step 2 (T): Open-Circuit U 2A 12V 4 8 8 5 Node analysis (mesh analysis would have been more natural!): 2A i2 i3 U 12V + 4 (2A-i2) = 21 i2 (12+8)V = 21 i2 + 4 i2 i2 = 20V/25 = 0.8A U = i25 = 5 4/5A = 4 V = UTeq 12V + 4 i3 = u1 (8+5+8) i2 = u1 2A = i2 + i3 u1 } { Step 2 (N): Short-Circuit I 2A 12V 4 8 8 5 i2 i1 Mesh analysis: i1 = 2A (4+8+8) i2 – 4 i1 = 0 20 i2 = 4 2A i2 = 1A = INeq Check: UTeq = INeq Req 4V = 1A 4 Voltage Divider Real Op-Amp Parameters: (±) 5-24 Vsupply voltage VEE,VCC 010-100 output resistance Rout 106-1013 input resistance Rin 105-108open loop gain A idealtypicalParameter equivalent circuit +VCC -VEE Negative/Positive Feedback • output to non-inverted input positive feedback • output to inverted input negative feedback Voltage Follower: input voltage = output voltage !!! input current = 0 !!! output resistance very small it acts as a buffer isolates the load from the source Is it useful ??? Uout Uin Wouldn’t it be nice… Stay where you are… responds to tenths of μV unstable !!! Schmitt Trigger Uin Uo R3 R2 R1 ux +Vs -Vs Case 2: Uo -Vs ux < Uin Case 1: Uo +Vs ux > Uin Hysteresis +Vs???-Vs ux1< Uinux2< Uin<ux1Uin<ux2 coming from below coming from above u x1 = V s R 2 R 3 R 1 R 3 + R 1 R 2 R 1 R 2 +R 2 R 3 +R 1 R 3 u x2 = V s R 2 R 3 R 1 R 3 R 1 R 2 R 1 R 2 +R 2 R 3 +R 1 R 3 Digital Electronics: (circuits that deal with 0s and 1s) digital information: transmit without noise!!! electronic states: HIGH LOW either or Boolean states: TRUE FALSE H L 1 0 digital input digital output: - combinational tasks gates - sequential tasks flip-flops Boolean Algebra: A • 1 = A A + 1 = 1 A • 0 = 0 A + 0 = A A • A = A A + A = A A • A = 0 A + A = 1 A = A A • B = B • A A • (B • C) = (A • B) • C A • (B + C) = A • B + A • C A + B = B + A A + (B + C) = (A + B) + C A + B • C = (A + B) • (A + C) (AND precedence over OR…) De Morgan: A + B = A • B A • B = A + B A + A • B = A A • (A + B) = A A + A • B = A + B A • (A + B) = A • B Absorption laws: 3 Input Karnaugh Maps, e.g.: 1111 1011 1101 0001 0110 1010 0100 0000 QCBA 1.) Make K-map: - inputs on two axes - only one bit changes! a.) 11001 01100 10110100C\AB c.) … 1 0 10110100B\ACb.) 0 1 00 1 0 1 1 4 Input K-Map: 110010 100011 110001 110000 10110100CD\AB a.) 1s or 0s ? 1s !!! b.) groups: 110010 100011 110001 110000 10110100CD\AB Good: Q = AC + AB + AD Better ?: Q = A(BCD) State Machines forward voltage drop 0.7 V reverse current ~ nA reverse breakdown voltage 70 – 100 V (or Zener) Diode Characteristics: A formula: e = electron charge k = Boltzman constant T = absolute Temperature n = parameter Si 1.5 < n < 2 I0 10 -8 A I = I 0 e e kT V n - 1 Steady State: t : U(t) const How to figure out which voltage/current it adjusts to? KVL & KCL !!! • resistor - current & voltage adjust: Ohm’s law - time scale: instantaneous • capacitor - voltage adjusts, current 0 - time scale: building up the electric field (voltage) • inductor - current adjusts, voltage 0 - time scale: building up the magnetic field (current) V = RI I = C dV dt V = L dI dt Complex Arithmetic: (x1 + jy1) ± (x2 + jy2) = (x1 ± x2) + j(y1 ± y2) (x1 + jy1)(x2 + jy2) = (x1x2 – y1y2) + j(y1x2 + x1y2) r1exp(j 1)r2exp(j 2) = r1r2exp(j( 1+ 2)) Addition/Subtraction: Multiplication: Division: z1 z2 = x1 + jy1 x2 + jy2 = x1x2 + y1y2 x2 2 + y2 2 + j x2y1 - x1y2 x2 2 + y2 2 = r1 r2 e j( 1 2 ) Phasors: V(t) = V cos( t + ) = Re(Vej ej t) V = Vej = V V’(t) = V’ sin( t + ) = V’ cos( t + - 90o) V’ = V’ ( 90o) Idea: use one complex number to represent a (co-) sinusoidal functional dependence: Note: Phasor arithmetic requires a unique frequency ( ) ! The ej t time dependence is implicitly still present! Phasor: - drops the time dependent part - highlights magnitude and phase - summarizes them as one complex number The idea that the sinusoid is the real part of the phasor times ej t requires the sinusoid to be brought into cosine form: Time Domain vs. Phasors: I(t) = I0cos( t+ ) time domain representation I = I( ) = I0e j Phasor representation - I0sin( t+ ) = I0cos( t+ +90 o) = Re( I0e j tej ej90) = Re( j Iej t) 1I0sin( t+ ) = 1I0cos( t+ -90 o) = Re( j-1 -1Iej t) d/dt dt time domain j 1/(j ) frequency domain dI dt = Idt = Ex. Continued: V1 I V2 Vo 2H 1 4 0.1F The 2A, 5rad/s source ( =-90o): vo2 = 1 V1/Z = 2.50e -j30.8 j L = j2H5rad/s = j10 1/(j C) = -j/(0.1F5rad/s) = -j2 Vo(t) = [-1 + 2.50cos(2t rad/s – 31 o) + 2.33sin(5t rad/s + 12o)]V -v o1 = 1 1+ 4 5V =1V ZR = 1 + 4(-j2) 4 - j2 = (1.8 - j1.6) IR = j10 j10+ ZR I = j10 j10+ ZR 2e-j90A vo3 =1 IR = j10 1.8+ j8.4 (-j2)V = 2.33e-j77.9V Phasor Diagrams: VR VL VC Vmax VL - V C (also currents!) Vmax = VR 2 + (VL VC ) 2 tan = VL VC VR Power in an AC circuit: • P = Re(I) Re(V) = IrmsVrmscos( ) • no power lost in L or C !!! • power factor (pf): cos( ) Bode Plot Sketches: 1st decompose: 2nd put together graphically: K 20log10K 0o - + +n90o -n90on20dB /decade +n180o n40dB /decade + n20dB /decade +n90o+ -n180o - -n90o - Gain & Phase G(s) = KA1(s)A2(s)KAn (s) s±n s+ ±n s2 + 2 n s+ n 2 n 2 ±n Active Filters RinC Vin Rfb VO + _ + _ Vin VO C Rfb + _ + _ Rin low-pass filter: high-pass filter: Active filters 2: Vin R1 R1 C1 C2 R2 Ri Rfb VO + _ + _ Vin R1 R1 C1 C2 R2 R2 Rfb Ri VO + + _ _ band-reject filter: (“OR” logic) band-pass filter: (“AND” logic) Different Small Signal Equivalents: r = (1+hfe)re hfere hfeib = hfevbe/r = gmvbe npn, active: iC = IS(e vBE VT -1) ISe vBE VT diC dvBE iC VT diC dvBE = ic vbe gm = 1 re ICQ VT ICQ 26mV re = vbe ib +hfeib = vbe (1+hfe)ib = r? 1+hfe r hfe = 1 gm Problem 9.12: Small Signal Equivalent Given: hfe = hFE = 100 ICQ = 10mA ac equivalent: small signal equivalent: Wanted: a.) gm b.) re c.) Rin d.) Av (npn) BJT FET (n-channel) Collector, Base, Emitter Source, Gate, Drain controlled by iB iC = iB iG = 0 (!!!) vBE = 0.7V (or 0.8V or <0.5V…) controlled by vGS: depletion & JFET: enhancement: saturation: ohmic: vBE = 0.8V, iC < iB, vCE = 0.2V vDS < vGS – Vp, iG = 0, vDS < vGS – Vt active: saturation: iD = IDSS(1-vGS/Vp) 2 iD = K(vGS-Vt) 2 cut-off pinch-off cut-off vBE < 0.5V iC = iB = 0 vGS Vp iD = iG = 0 vGS Vt i D = IDSS 2 I VGS VP VDS V P VDS VP 2 iD = K 2 VGS Vt( )VDS VDS 2[ ] MOSFET Summary: depletion MOSFET = JFET VDS = VGS – VT enhancement MOSFET: Saturation or Active region: Triode or Ohmic region: simplified: typically: 0.01V-1< <0.1V-1 again: VDS << 1 iG = 0 iD = K 2 VGS Vt( )VDS VDS 2[ ] iD = 2K VGS Vt( )VDS rDS = VDS iD 1 2K VGS Vt( ) iD = K VGS Vt( ) 2 1+ VDS( ) iD = K VGS Vt( ) 2 Regions Boundaries (n-channel): JFET/MOSFET: VDS = VGS – VP iD = (IDSS/VP 2)VDS 2 cutoff: VGS < VP ( iD = 0) enhancement MOSFET: VDS=VGS – VT iD = KVDS 2 cutoff: VGS < VT ( iD = 0) ~ R ip = K (tgs — V,,)* Extraneous D GS ~ “to. \ root \ \ Q point \ \ - Ing } —-—-—-—--—= Vg = UG + Rstp \ | (Bias line) \ | : | \ \ | . | =F t UGS Yo ‘Ves VG (illustrations from A.R. Hambley: Electrical Engineering; Pentrice Hall)