ECE 495/595 Lab Assignment 5: Building a Hardware DFT using PPC and LABVIEW, Assignments of Electrical and Electronics Engineering

Download ECE 495/595 Lab Assignment 5: Building a Hardware DFT using PPC and LABVIEW and more Assignments Electrical and Electronics Engineering in PDF only on Docsity! LAB Assignment #5 for ECE 495/595 Assigned: Tue., April 14, 2009 Due: Tue., April 21, 2009 Description: Build a hardware DFT that uses the communication mechanism and LABVIEW code from previous labs. Transfer the y integer values of the waveform to the PPC using LABVIEW, compute a ‘hardware’ DFT using the PPC to ‘serve’ data to the hardware and send the values back to LABVIEW for conversion and viewing. You can use the LABVIEW code you developed in lab #3 for sending the data and retrieving the results to the PPC directly. You will also use the scanf and printf loops in the C code that runs on the PPC from that lab. Instead of carrying out a software DFT, however, you will implement the DFT as a state machine in the reconfigurable logic. You will use the CoreGen to instantiate a Sin and Cos core within ISE to serve as the lookup table for the sine and cosine functions. 1) Under ‘programs/ISE xx/accessories’, click on ‘CORE Generator’ 2) Select ‘new project’ under the file menu 3) Enter a name and directory 4) In the CGP form, select Virtex2P, xc2vp30, ff896, -7. Click Ok. 5) Expand Basic Elements in the list on left in CORE Generator, then Math Functions, then Trig Functions. 6) Select Sine-Cosine Lookup 7) Click Customize and name the component SinCos. 8) Set Output Width to 14 and THETA Input Width to 9, select Function “Sine and Cosine”, leave Memory Type “Distributed ROM”, click next. 9) Leave options at defaults on next screen (“Non-registered and Symmetric”), click next 10) Unclick “Handshaking”, click Generate. Once the CORE Generator finishes, you need to copy the .vhd file to your pcores/xxx/src/hdl/vhdl directory and the .ngc file to pcores/xxx/devl/pro- jnav directory. When you run EDK, you need to copy the .ngc file into the implementation directory. (Perhaps there is a better way -- I’m all ears!) The filename with extension ‘.vho’ has a template for the module that you can cut-and-paste into your VHDL file with the FSM. You’ll need to change the names in parenthesis to match those you use in your code. Your state machine needs to implement the DFT C code from lab #31: for ( j = 0; j < num_pts/2; j++ ) { real[j] = 0; imag[j] = 0; 1. NOTE: The full transform actually needs num_pts/2 + 1 points in the frequency domain, so we are not computing the highest frequency component using this formulation. Also, the imag components should be negated but we fix with this later when converting to magnitude and phase. for ( i = 0; i < num_pts; i++ ) { real[j] += y_data[i]*GetCos(i*j); imag[j] += y_data[i]*GetSin(i*j); } } My state machine uses 8 states with the following definitions ********************* IMPORTANT (4/22): I developed my state machine to work with the Bus Master, NOT the client server, so your state machine may require a couple more states -- see IMPORTANT notes below. ********************** start_state: Wait for num_pts to be placed in the Value register (see lab #4) -- save this number a num_pts_register. Wait for the ‘command’ bit to be set to ‘1’. Once set, goto out_loop_state. out_loop_state: If j is equal to num_pts_register/2, goto done. Else set real and imag registers to 0 and goto in_loop_state. in_loop_state: Compute i*j and save in a register (you need carry out the operations in the loop body in stages or you will end up violating timing constraints). Issue a read command for the data value at y_data[i] and goto sin_cos_state. sin_cos_state: Wait for read to complete. Once completed, save the y_data value as well as the sin and cos values present on the output buses of the SinCos core into registers. Goto accum_state. accum_state: Create signed versions of the y_data, sin, cos, real and imag register values. Add to the real and imag registers the products y_data*cos and y_data*sin where these arguments are the signed versions. The output of the SinCos core is a signed value -- you MUST tell the synthesis engine this otherwise you’ll get incorrect results. Goto inc_i_state. inc_i_state: If i+1 = num_pts_register, reset i and goto write_state. Else add 1 to i and goto in_loop_state. write_state: Write both the real and imag register values to location j. You may need to add a control bit to the Command register to indicate which array to write. Or you can add num_pts_register/2 to the j index for the imag index location. In this case, be sure to declare a single array, real_imag[num_pts], in the C code. Finally, increment j and goto out_loop_state. done_state: Write Command register with done command, and loop forever. IMPORTANT (4/21/09): If you use my example code for lab #4, then you will need to add a ‘clear’ command, otherwise consecutive read commands will not be processed because the C code triggers ONLY on a change to the command register. For consecutive reads, the command register does not change and so only the first read will be processed. To handle this, add a clear command: go_bit <= slv_reg0(31); get_bit <= dft_command(30); put_bit <= dft_command(29); done_bit <= dft_command(28); clear_bit <= dft_command(27);