Laboratory Experiment 4 on Power Factor Correction | ECE 225, Lab Reports of Electrical Circuit Analysis

Download Laboratory Experiment 4 on Power Factor Correction | ECE 225 and more Lab Reports Electrical Circuit Analysis in PDF only on Docsity! Boise State University Department of Electrical and Computer Engineering ECE 225L – Circuit Analysis and Design Lab Experiment #4: Power Factor Correction 1 Objectives The objectives of this laboratory experiment are: • to calculate and measure complex power, observe lagging power factor, and correct lagging power factor by adding capacitive compensation. 2 Theory The apparent power or voltamperes (VA) in a given circuit is the product of the rms voltage and rms current magnitudes. The real power (also referred to as average power or active power) is the apparent power times the cosine of the angle between the voltage and the current waveforms or phasors. This cosine term is known as the power factor, and it is desirable to operate at or near unity power factor. This is the case since equipment costs are largely proportional to conductor size and insulation, which are determined by the voltamperes required. Also, low power factor operation implies high current with resulting small useful work. This is clear since a purely inductive load may draw a large current and thus large voltamperes demand. The real power lost in the transmission or distribution line feeding this load could be substantial. These |Ĩ|2R losses are costly to utilities and large energy consumers. It is common to add capacitive reactance to an inductive circuit in order to bring the voltage and current in phase (and thus bring the power factor to unity). This practice is known as power factor correction. Clearly, power factor correction can reduce the cost of electric power system operation and can permit generators to produce more active power at rated kVA. In order to maintain a higher voltage at the load, and reduce line losses, the correction should always be made at the load rather than the source. V ~ C Z = R + jX − P + jQ jQ C L L P + jQ S S S R jX L jX − + Figure 1: Capacitive Compensation at Load End 1 Without the shunt capacitor in dotted lines and in parallel with the load, the source must supply both real power PL and reactive power QL to the load, thus resulting in high current, high voltage drop and high losses in the transmission line. When the capacitor is added as shown, the capacitor supplies reactive power to the load and thus relieves the source and line of this unnecessary load. As a load, a capacitor has zero power factor leading, thus making its reactive power consumption negative (i.e., it generates reactive power). If the capacitors were shunted at point 1 instead of point 2, the compensation would still relieve the source of the unnecessary reactive power QL of the load, but the line would still carry the full PL + jQL, thus still causing substantial voltage drop and line losses. The convention used for leading and lagging power factor is standard. When computing the power factor of a load (assuming load notation with the current entering the + terminal), the power factor is lagging if 0o < φ < 180o (i.e. current lags voltage), and leading if −180o < φ < 0o (i.e. current leads voltage). Note that for passive RLC loads, −90o ≤ φ ≤ 90o. 3 Equipment • OrCAD PSpice Version 9.1 or 9.2. 4 Procedure jX 2 R 2 I ~ 1 V 2 ~ + − V ~ 1 jX C R 1 I ~ 2 1 + − jX Figure 2: AC Study Circuit 1. Build the AC circuit shown in Figure 2 using a 60-Hz, 120-Vrms source (peak voltage of 120 √ 2 or 169.7 volts) delivering real and reactive power to a series RL-load with values R2 = 100 Ω and L2 = 265 mH through a transmission line with values R1 = 10 Ω and L1 = 26.5 mH. Assume initially that there is no shunt capacitor. (In the PSpice circuit, use a value C = 0.001 µF to represent a nearly perfect open circuit.) 2. Simulate this system without compensation for 100 ms and display only the last 50 ms. Use a maximum time step of 0.01 ms. This will give you smoother sine responses. Place voltage 2