Laboratory Work on Computer Architecture I | CS 470, Lab Reports of Computer Science

Download Laboratory Work on Computer Architecture I | CS 470 and more Lab Reports Computer Science in PDF only on Docsity! CS470 – Computer Architecture I Last Updated - 05/08/02 Course Manager - Virgil Bistriceanu, Instructor 3 credit hours; elective for CS, required for CPE; 100 min. lecture & 100 min. lab each week Current Catalog Description - Introduction to the functional elements and structures of digital computers. Detailed study of specific machines at the register transfer level illustrates arithmetic, memory, I/O, and instruction processing. Prerequisites: CS 350 and ECE 218. (2-2-3) Textbook • David A. Patterson, John L. Hennessy, Computer Organization and Design: the hardware/software interface, second edition, Morgan Kaufmann, Inc. 1994, ISBN 1-55860-491-X References - other textbooks or materials • Harvey G. Cragon, Memory Systems and Pipelined Processors, Jones and Bartlett, 1995, ISBN 0-86720- 474-5 • Michael J. Flynn, Computer Architecture, Jones and Bartlett, 1995, ISBN 0-86720-204-1 • Vincent P. Heuring, Harry F. Jordan, Computer Systems Design and Architecture, Addison Wesley, 1997, ISBN 0-201-89589-7 Course Goals Students should be able to: • Present the milestones of computer architecture history • Fundamentals of computer design o Explain the difference between various measure of performance: Latency, throughput; MIPS, MPFLOS o Comparing performance o Utilize Amdahl’s law to estimate the overall speedup o Explain the difference between a good and a bad benchmark • Assembly level machine organization o Explain the basic organization of the classical von Neumann machine and its major functional units o Explain how an instruction is executed in a classical von Neumann machine o Summarize how instructions are represented at both the machine level and in the context of a symbolic assembler o Explain different Instruction Set formats (0 (stack), 1 (accumulator), 2, and 3-addresses per instruction; Variable length vs. fixed length formats) o Design the Instruction Set for a general purpose CPU o Explain how the basic addressing modes work: Register, Memory direct, Memory indirect, Base and displacement, Indexed o Explain how base and displacement addressing is used in block-based programming languages o Write small MIPS assembly language programs o Demonstrate how fundamental high-level programming constructs are implemented at the machine-language level: If-then-else, Loops (for, while, do-until), Procedure call/return o Explain the basic concepts of interrupts and I/O operations • Datapath and Control o Design a single clock-cycle datapath for a CPU o Explain why a single clock-cycle datapath is inefficient o Re-factor a single clock-cycle datapath into a multi clock-cycle one o Explain the difference between a hardwired and a microprogrammed control unit o Design the control unit for a single clock-cycle datapath o Explain how exceptions impact the design and performance of a datapath • Pipelining o Derive the formula for the throughput of an ideal pipeline with N stages o Explain the limiting factors in building a pipeline with too many stages o Explain how data and control hazards occur and how their impact can be eliminated or reduced o Re-factor MIPS code to reduce/eliminate data and branch hazards o Explain the significance of a late commit in the pipeline o Explain the changes in the design and implementation of a pipelined datapath to account for exceptions o Explain branch prediction o Solve problems that require finding the real CPI of a program running on a pipelined datapath • The memory hierarchy o Identify the main types of memory technology and explain the trade-off in using them o Explain the effect of memory latency on running time o Explain the use of memory hierarchy to reduce the effective memory latency o Explain the differences between different cache organizations: Direct mapped, Set associative Fully associative o Utilize a cache simulator and access traces to compare the performance of caches with different sizes and organizations o Explain main memory organization alternatives to improve performance: Wide-memory, Interleaving o Explain the impact of access stride to performance o Explain the virtual memory structure and mapping o Explain why and how virtual memory impacts performance and how performance can be improved. TLB o Analyze the differences between cache organizations in systems with virtual memory: Real address caches, Pipelined real caches, Virtual address cache, Restricted virtual caches, TLB addressing • I/O o Define the meaning of various I/O performance measures o Types and characteristics of I/O devices o Explain the differences between major buses (IDE, SCSI, USB, PCI): synchronous v. asynchronous, Serial v. parallel, Number of devices, Termination, Transfer rates o Design issues related to I/O system addressing: Memory-mapped I/O, Cache coherency, Snoopy controllers, DMA I/O configurations o Explain the sources of latency in a I/O subsystem Prerequisites by Topic • Basic understanding of a von-Neumann computer organization • The ability to explain the differences between a high level instruction and a compiled instruction • Knowledge of the steps involved in the execution of an instruction • Solid understanding of basic building blocks for a datapath: ALU, register, counter, multiplexer, decoder, glue logic • Working knowledge of Boolean logic Major Topics Covered in Course