Language Two - HDL Design - Lecture Slides, Slides of Verilog and VHDL

Download Language Two - HDL Design - Lecture Slides and more Slides Verilog and VHDL in PDF only on Docsity! Language Overview II The continuation of a grand tour of the language. Docsity.com Elements Covered in II • Reminder from I: Language overview lectures do not cover all aspects of the language. But they do cover a large portion of it. • Concurrent Statements • Sequential Statements – In Part I covered: TYPES, Declarations, operators, and structural architectures, i.e., component instantiation – a concurrent statement Docsity.com Component Instantiation • Consider that the following is already analyzed and in your library – ENTITY wigit IS • PORT(p1, p2 : IN BIT); – END wigit; – ARCHITECTURE Y OF wigit IS …..; – ARCHITECTURE Z OF wigit IS …..; Docsity.com Component Instantiation • Then the declaration for use is • ARCHITECTURE use_it OF xyz IS – COMPONENT wigit • PORT(p1, p2 : IN BIT); – END COMPONENT: – -- and the configuration is – FOR C0 : wigit USE ENTITY work.wigit(y); – FOR OTHERS : wigit USE ENTITY work.wigit(Z); Docsity.com And use in the architecture – SIGNAL A,B,C,D ; BIT; • BEGIN – CO : wigit PORT MAP (A, B); – C1 : wigit PORT MAP (p1 =>C, p2=>D); • Component Instantiation is a Concurrent Statement Docsity.com Block example – example_blk: BLOCK (clk= ‘1’ and clk’event) – BEGIN – Z <= guarded Q1; – X <= guarded Q0 AND B; – Y <= Q3; – END BLOCK example_blk; • Note that Z and X are guarded signal assignment statements • Scheduling of a new value for Z and X occurs only when the guard is TRUE and a signal on the right hand side has an event while the guard is true Docsity.com Concurrent Statements • PROCESS STATEMENT – [process_label:] – process [ (sensitivity_list) ] – process_declarative_part – begin – process_statement_part -- {sequential statement} – end process [process_label]; Docsity.com Process Statement – process_declarative_part::= – subprogram_body – type_declaration – subtype_declaration – constant_declaration – variable_declaration – file_declaration – alias_declaration – attribute_declaration – attribute_specification – use_clause • The contents of a process will be covered further in Sequential Statements (i.e. what goes between BEGIN-END) Docsity.com Concurrent Statements • Compound Waveforms – ; --ends the waveform – , --separates waveform elements that are generated at the same time – Z <= ‘0’ AFTER 4 NS, ‘1’ AFTER 10 NS, – ‘0’ AFTER 14 NS, ‘1’ AFTER 20 NS; Docsity.com Concurrent Statements • Compound Waveforms – ; --ends the waveform – , --separates waveform elements that are generated at the same time – Z <= ‘0’ AFTER 4 NS, ‘1’ AFTER 10 NS, – ‘0’ AFTER 14 NS, ‘1’ AFTER 20 NS; t + 2 0N S t + 1 4N S t + 1 0N S t + 4 N St Docsity.com Concurrent Statements • Conditional Signal Assignment Statement – target <= waveform_1 WHEN condition_1 ELSE – waveform_2 WHEN condition_2 ELSE – waveform_3 WHEN condition_3 ELSE – • • • – waveform_n-1 WHEN condition_n-1 ELSE – waveform_n; • Waveforms 1 through n are only a single waveform. Compound waveforms not allowed. • WHEN conditions are Boolean expressions Docsity.com Sequential Statements • Sequential Statements are like the statements of any procedural programming language. • They are executed sequentially according to the control flow of the code. • Time introduced using special language statements. Docsity.com Sequential Statements • Those statements allowable between the BEGIN and END of a PROCESS • WAIT Statement – wait [sensitivity_clause] [condition_clause] – [timeout_clause] – sensitivity_clause::= on sensitivity_list – WAIT ON A,B; – sensitivity_list::= signal_name {,signal_name} – condition_clause::= until condition – WAIT UNTIL A=‘1’; – condition::= boolean_expression – timeout_clause::= FOR time_expression – WAIT FOR 20 NS; Docsity.com Sequential Statements • Assert Statement • Signal Assignment Statement (Sequential) <= exactly like a concurrent one only context makes it sequential • Variable Assignment Statement := • Procedure Call Statement Docsity.com Sequential Statements • LOOPS – [loop_label:] [iteration_scheme] loop – sequence_of_statements; – end loop [loop_label]; – iteration_scheme::= while condition | – for loop_parameter_specification – loop_parameter_specification::= – identifier in discrete_range Docsity.com Loop Examples • while A /= ‘1’ loop • sequence_of_statements; --at least one • -- sets A • end loop; • my_loop : for I in 1 to 100 loop • sequence_of_statements; • end loop my_loop; • for OP in OPAND to OPMOVE loop … Docsity.com Sequential Statements • NEXT STATEMENT – NEXT [loop_label] [when condition]; – If the condition is true causes termination of the current iteration of the loop and the start of the next iteration. • EXIT STATEMENT – EXIT [loop_label] [when condition]; – Causes exit from the loop when the condition is true. Docsity.com