Understanding Latches, Flip-Flops, and Bit Storage in Digital Logic, Slides of Computer Aided Design (CAD)

Download Understanding Latches, Flip-Flops, and Bit Storage in Digital Logic and more Slides Computer Aided Design (CAD) in PDF only on Docsity! Latches & Flip-Flops Docsity.com Combinational Logic (Review) • Changes in input values are reflected immediately (subject to the speed of light and electrical delays) on the outputs • Each gate has an associated “electrical delay” • Delays are often ignored for the purpose of the logic design (but not for the real implementation!) • As soon as inputs change, the outputs change – no memory of what happened before – (at least conceptually) Docsity.com Master-Slave D Flip-Flop • A state element that is edge-sensitive – Want changes in output ONLY on the transition of the Clk signal from 0  1 (or from 1  0) D Q Q positive edge-triggered flip-flop Docsity.com Timing of Master-Slave D Flip-Flop • Changes to Q occur only on the positive edge of the Clock D Clock Q D Q Q positive edge-triggered flip-flop time  Docsity.com Registers – A flip-flop stores one bit of information – When you want to store n bits  register • n flip-flops used • Clock is shared by all so action is synchronous with clock edge – Some common register types • Simple register • Shift register • Parallel access shift register • Lots of counters: up counter, down counter, BCD counter, ring counter, Johnson counter Docsity.com