Latches and Flip-Flops - Digital System Design - Lecture Slides, Slides of Digital Systems Design

Download Latches and Flip-Flops - Digital System Design - Lecture Slides and more Slides Digital Systems Design in PDF only on Docsity! Latches & Flip-Flops Docsity.com Example Needing Bit Storage  Flight attendant call button  Press call: light turns on  Stays on after button released  Press cancel: light turns off  Logic gate circuit to implement this? Q Call Cancel Doesn’t work. Q=1 when Call=1, but doesn’t stay 1 when Call returns to 0 Need some form of “feedback” in the circuit a a Bit Storage Blue light Call button Cancel button 1. Call button pressed – light turns on Bit Storage Blue light Call button Cancel button 2. Call button released – light stays on Bit Storage Blue light Call button Cancel button 3. Cancel button pressed – light turns off Docsity.com Basic NOR Latch Redrawn Q Q R S S R Q Q 0 0 0/1 1/0 0 1 0 1 1 0 1 0 1 1 0 0 memory state Docsity.com Timing Analysis of Basic Latch  What happens at t10??  S and R both go from 1 to 0 simultaneously  If gate delays are exactly the same  oscillation!!! 1 0 1 0 1 0 1 0 R S Q Q ? ? t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 Q Q R S Docsity.com Gated SR Latch  To get better control of the state changes, we must limit when the input signals affect the outputs  Outputs change only when Clk = 1  Clk acts as an Enable signal Q Q R S Clk Clk S R Q(t+1) 0 x x Q(t) 1 0 0 Q(t) 1 0 1 0 1 1 0 1 1 1 1 x undefined since we don't know which stable state will result Docsity.com D Latch Timing Diagram  Output Q changes only when Clk = 1  Q tracks D when Clk = 1  This latch is level-sensitive since the output is sensitive to the level of the clock t 1 t 2 t 3 t 4 Time Clk D Q Docsity.com Master-Slave D Flip-Flop  Desire to remove the level-sensitive nature  Want changes in Q only on the transition of the Clk signal from 1  0 (or from 0  1)  When Clock = 1, master D latch tracks D; slave D latch remains unchanged (Q remains fixed)  When Clock = 0, master D latch is unchanged; slave D latch tracks Qm D Q Q Master Slave D Clock Q Q D Q Q Q Clk Clk D Q Q negative edge-triggered flip-flop Docsity.com Timing of Master-Slave D Flip-Flop  Changes to Q occur only on the negative edge of the Clock D Q Q Master Slave D Clock Q Q D Q Q Q m Q s Clk Clk D Clock Q m Q Q s = Docsity.com Simple 4-bit Register  A standard 4 bit register using D flip flops Q 3 Q 2 Q 1 Q 0 Clock Parallel input Parallel output D Q Q D Q Q D Q Q D Q Q Docsity.com 4-bit Register with Load Control  Controlling the load capability Q 3 Q 2 Q 1 Q 0 Clock Parallel input Parallel output D Q Q D Q Q D Q Q D Q Q Load Docsity.com