VLSI Design System: Layout and Combinational MOS Logic Circuits Design Approaches - Prof. , Study notes of Electrical and Electronics Engineering

Download VLSI Design System: Layout and Combinational MOS Logic Circuits Design Approaches - Prof. and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! EE534 VLSI Design System Summer 2004 Lecture 11:Chapter 7 Layout and Combinational MOS logic circuits design approaches Review: Construction of PDN NMOS devices in series implement a NAND function NMOS devices in parallel implement a NOR function A B A • B A B A + B Review: Equivalent inverter: effective width to length ratios (model I) For the NOR gate the effective width of the drivers transistors doubles. That means the effective aspect ratio is increased. For the NAND gate the effective length of the driver transistors doubles. That means the effective aspect ratio is decreased. . Parallel combination Series combination Review: CMOS NAND gate and its inverter equivalent Can we estimate switching threshold of the NAND gate by using CMOS inverter expression for the switching threshold? n p pTDD n p nT th K K VV k k V INRV + −+ = 1 )( )( ,, WN WN WP WP 2WP ½ WN n p pTDD p p nT th K K VV k k V NANDV 4 1 )( 4 )( ,, + −+ = 2KP Kn/2 If Kn=Kp, Vth=? Equivalent inverter: Worse case delay design consideration Represent complex gate as inverter for delay estimation Use worse-case delays Example: NAND gate Worse-case (slowest) pull-up: only 1 PMOS “on” Pull-down: both NMOS “on” WN WN WP WP WP ½ WN KP Kn/2 Review: CMOS NOR gate: design consideration A B A B n p pTDD n p nT th K K VV k k V INRV + −+ = 1 )( )( ,, n p pTDD n p nT th K K VV k k V INRV 4 1 )( 4 )( ,, + −+ = n p pTDD n p nT th KN K VV kN k V INRV 2 ,2, 1 )( )( + −+ = Two input For N inputs One input Wp/2 2Wn KP/2 2Kn Equivalent inverter Problems with equivalent inverter method: Need to take into account load capacitance CL - Depends on number of transistors connected to output (junction capacitances) - Even transistors which are off (not included in equivalent inverter) contribute to capacitance Need to include capacitance in intermediate stack nodes. Worse-case: need to charge/discharge all nodes Body effect of stacked transistors Complex CMOS logic gates Complex CMOS logic gates: Euler path method Layout: Euler path method A B C D E C E D BA Euler path: B→A→C→E→D B A C E D Vcc Gnd F F 1. Order transistors gates according to Euler path 2. Connect Vcc and Gnd 3. Make other connections according to circuit diagram Fan-In Considerations DCBA D C B A CL C3 C2 C1 Distributed RC model (Elmore delay) TpHL=0.69[R1C1+(R1+R2)C2+(R1+R2+R3)C3+(R1 +R2+R3+R4)CL] tpHL = 0.69 Reqn(C1+2C2+3C3+4CL) Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case. tp as a Function of Fan-In tpHL tpLH t p (p se c) fan-in quadratic function of fan-in linear function of fan-in Gates with a fan-in greater than 4 should be avoided. tp tp as a Function of Fan-Out 2 4 6 8 10 12 14 16 tpNOR2 t p (p se c) eff. fan-out All gates have the same drive current. tpNAND2 tpINV Slope is a function of “driving strength” Influence of Fan-In and Fan-Out on Delay VDD A B A B C D C D Fan-out: Number of Gates connected to the output in static CMOS, there are two gate capacitances per Fan-out Fan-in: Number of independent variables for the logic function, which has a quadratic effect on tp due to: resistance increasing capacitance increasing FOaFIaFIatp 3 2 21 ++= tp as a Function of Fan-In and Fan-Out Fan-in: quadratic due to increasing resistance and capacitance Fan-out: each additional fan-out gate adds two gate capacitances to CL tp = a1FI + a2FI2 + a3FO Fast Complex Gates: Design Technique 1 Transistor sizing as long as fan-out capacitance dominates Progressive sizing InN CL C3 C2 C1In1 In2 In3 M1 M2 M3 MN Distributed RC line M1 > M2 > M3 > … > MN (the MOSFET closest to the output should be the smallest) Can reduce delay by more than 20%; decreasing gains as technology shrinks Resistance of M1(R1) N times in the delay Equation. The resistance of M2(R2) appears N-1 times etc. Fast Complex Gates: Design Technique 2 Input re-ordering when not all inputs arrive at the same time C2 C1In1 In2 In3 M1 M2 M3 CL C2 C1In3 In2 In1 M1 M2 M3 CL critical path critical path 1 0→1 1 1 1 0→1 chargedcharged Fast Complex Gates: Design Technique 2 Input re-ordering when not all inputs arrive at the same time C2 C1In1 In2 In3 M1 M2 M3 CL C2 C1In3 In2 In1 M1 M2 M3 CL critical path critical path charged1 0→1 charged charged1 delay determined by time to discharge CL, C1 and C2 delay determined by time to discharge CL 1 1 0→1 charged discharged discharged Sizing and Ordering Effects DCBA D C B A CL C3 C2 C1 Progressive sizing in pull-down chain gives up to a 23% improvement. Input ordering saves 5% critical path A – 23% 3 3 3 3 4 4 4 4 4 5 6 7 = 100 fF