lecture notes of digital and analog electronics, Lecture notes of Digital & Analog Electronics

Download lecture notes of digital and analog electronics and more Lecture notes Digital & Analog Electronics in PDF only on Docsity! Computer Science notes ⇒ Introduction to Digital Circuit Design This minisite contains notes taken by Chris Northwood whilst studying Computer Science at the University of York between 2005-09 and the University of Sheffield 2009-10. They are published here in case others find them useful, but I provide no warranty for their accuracy, completeness or whether or not they are up-to-date. The contents of this page have dubious copyright status, as great portions of some of my revision notes are verbatim from the lecture slides, what the lecturer wrote on the board, or what they said. Additionally, lots of the images have been captured from the lecture slides. Digital Circuits • Constructed from discrete state components • Inputs and outputs can only have two possible states • They are called logic elements Logic states can be referred to as: 1 and 0; True and False; On and Off. All are equivalent to each other, but we tend to use 1 and 0 in this strand. Physical Representation of States Logic states are electrically represented by 2 voltage levels. For TTL, these voltage levels are approximately 5V and 0V. There are two representation conventions: positive logic and negative logic. In positive logic, 5V is logic 1 and 0V is logic 0. In negative logic, the inverse is true; 5V is logic 0 and 0V is logic 1. In this strand, we tend to use the positive logic convention. Voltages are in respect to earth. High is considered to be logic 1 and low is logic 0. Simple Gates AND out = A.B A B out L L L L H L H L L H H H OR out = A + B A B out L L L L H H H L H H H H NOT out = A A out L H H L Three-input gates Three input gates do exist, they are basically two 2-input gates chained together. NAND out = A.B A B out L L H L H H H L H H H L NOR All TTLs float high by default. Commutation A + B = B + A A.B = B.A Association A + B + C = A + (B + C) = (A + B) + C A.B.C = A.(B.C) = (A.B).C de Morgan's Theorem A + B = A.B A.B = A + B Some Logical Manipulation A.(B + C) = A.B + A.C (A + B).(C + D) = A.C + B.C + B.D + A.D A.B + A.B = A.(B + B) = A A.(A + B) = A + A.B = A.(1 + B) = A XOR C = A.B + A.B De Morgan's Law Y.Z = Y + Z Terminology Product Term A single variable or logical product of several variables. E.g., A, X, A.B.C. This is basically the AND function. Note that A.B.C is not a product term. Sum Term Sum term is the single variable or the logical sum of several variables. The variables may be in true, or complemented, form. E.g., A + B + C, etc... This is the OR function. Note that here also, A + B + C is not a sum term. Sum-of-products This is product terms added together., e.g., A.B.C + Q.R.S + A.Q. Note that A.B.C + X.Y.C is not a valid sum-of-products form. Product-of-sums This is the sum of several terms multiplied together, e.g., (A + B + C).(X + H + J). Note that (A + B + C).(C + D) is not in product of sums form. Canonical Forms The first canonical form If each variable is in the true of complimentary form and it appears in each term of the sub- products, then it is known as the canonical sum-of-products and each term is a minterm. The second canonical form This similar to the first canonical form, but each variable in a product-of-sums form and each term becomes a maxterm. Minterm A minterm is a product term which contains each variable in complimentary form. When used in the canonical sum-of-products, the minterm represent an input condition that causes the output to be 1. Maxterm A sum term which contains each variable in complimentary form. When used in the canonical product-of-sums the maxterm represents an input condition which causes the function to be 0. Karnaugh Map This is based on boolean algebra and is another method of minimisation. C\AB 00 01 11 10 0 0 0 0 0 1 1 0 1 0 The order of bits on the top row is important. Only one bit can change between columns. This is essentially a re-arranged truth table. Variables which appear together horizontally or vertically are logically adjacent. If there are 2n maxterms, n is the number of rows that can be looped. The member of grouped minterms must be a power of 2. • Make loops as big as possible • Choose fewest loops possible • Include all minterms 2n minterms are logically adjacent if there are n bits changed. Five and six variable karnaugh maps can occur - these are represented in 3 dimensions. E CD\AB 00 01 11 10 00 1 1 01 11 10 1 1 E CD\AB 00 01 11 10 00 1 1 01 11 10 1 1 1 E is on top of E. The same applies to a six-variable Karnaugh Map, which looks like this: Which hardware implementation to use? PCB, IC, PLD? Which device technology? TTL, CMOS transistors, ECL? Hardware environment? Temperature, radiation, pressure, vibrations, etc... You need to minimise gates and packages, the gate layers (circuit delay), the number of interconnects between gates and between packages, maintenance costs, power consumption, weight, design costs, production costs, hazardous behaviour. Design Steps Check each stem! 1. Obtain requirements - an imprecise statement of objectives 2. Map requirements into a formal specification - truth table, etc 3. Design the circuit - use minimisation 4. Realise the circuit - consider any further minimisation 5. Analyse the circuit - either by hand or on computer. Allow for production and environmental consideration. 6. Prototype the circuit - check it on the lab under full range of conditions 7. Test Electrical Considerations Logic Families Standard spec (e.g.,) Military spec (e.g.,) Old Standard SN7400 SN5400 High Speed SN74H00 SN54H00 Low Power SN74L00 SN54L00 Schottky SN74S00 SN54S00 Low Power Schottky SN74LS00 SN54LS00 Advanced Schottky SN74AS00 SN54AS00 Advanced Low Power Schottky SN74ALS00 SN54ALS00 Temperature ranges: Standard: 0 °C - 70 °C; Military -55 °C - 125 °C Power Supply Gates are supplied by power from a power supply via a power rail known as Vcc and ground. This power rail is implied and not actually show on circuit diagrams. In a dual-inline package, powering the package automatically powers all the gates. Normally, the power supply is 5 V. For standard specification gates, the allowed variances are ±0.25 V and for military this is ±0.5 V. There is also an absolute voltage rating, above which the gate burns out. This is approximately 7 V. Totem Pole Output Output is high when Q1 is on and Q2 is off, inversely, output is low when Q1 is off and Q2 is on. During transitions, Q1 and Q2 both conduct, but current is limited by R1, this causes a "spike" to be seen on the supply rail and is known as electrical noise. The spike is caused by the sudden increase and then decrease in current required by the gate. Capacitors are evenly spread around a PCB according to some in-house rule of thumb. These "decoupling" capacitors are connected between supply rail and earth, supplying instantaneous current which the transistors need. Fan-out When the interconnecting node is low, current flows out of the second gate into the first one. The inverse happens when the interconnect is high. In a data book, the following notations are used to signify currents: • IOL - output when low • IOH - output when high • IIL - input when low • IIH - input when high Unused Inputs NAND and NOR gates can be used as inverters. 4-input gates can be used by 2 variables only, etc... However, TTL inputs float high and CMOS floats low. For a TTL 4-input AND: ABC1 = ABC, but for a 4-input OR: A + B + C + 1 = 1, which is a tautology. Unused inputs are susceptible to electrical noise and may slow down gate operation. This is two different ways to make a 3-input gate work with two inputs (generating logic 0). The bottom method is preferred. To generate logic 1, you can do something like this: The bottom circuit can only be used with low-power Schottky, however. For other devices, you can tie them to the Vcc rail using a 1k Ω resistor. TTL Voltage Levels The value of R is calculated according to a formula specified by the manufacturer. The value must be re-calculated every time an input or output is added or removed. Wired-AND Gate You can also do things like this to emulate AND gates: Which, by inspection, gives us an AND gate. Tristate Devices Tristate devices have 3 output states • TTL logic 1 state • TTL logic 0 state • A high-impedance state A tristate device can sink and drive large currents than TTL. Bus Driver/Receiver Of all the gates connected to a bus wire, only one should drive at once. All gates can be in a high impendence state, however. Representation This is a bidirectional bus This is a unidirectional bus. The number represents the bus width. Signals takes a finite time to propagate and are therefore comparable to gate delay. Characteristic Impedance Z0 = v / i Z0 PCB tracks 50 - 150 Ω Twisted pair 100 - 120 Ω Coaxial cable 50 - 75 Ω Multiplexing and Demultiplexing A multiplexer switches from various inputs to an output, e.g., a mechanical one may be an input selector on a hi-fi amplifier. An electrical multiplexer: offers one logic load, have normal fan out, and have a strobe to enable/disable the mux (multiplexer). A demultiplexer does the opposite - it puts an input onto the addressed output. Programmable Logic Devices PLDs have an inverting stage, an ANDing stage and an ORing stage. They have multiple I/Os and they realise sum-of-product expressions. A programmer is a device to which an unprogrammed PLD is plugged. Using a programmer keyboard and a schematic of the device, internal connections can be located and blown away. Traditionally the method for doing this is: 1. Create boolean equations 2. Enter them into computer program 3. Compile them into JEDEC form 4. Programmer uses JEDEC file to program the PLD. PROMs are general purpose decoders leading to an ORing stage. Only the ORing stage is programmable. PROMs are available in different varieties, such as: • ROMs are programmed by the manufacturer, and are only cost-effective if manufactured in large quantities. • PROMs are developed in a lab. Once the fuses are blown, they can't be reinstated. They are programmed by electrical pulses up the output. • EPROMs, this are like PROMs, but UV light resets the fuses. • EEPROMs, like EPROM, but electrical pulses are used to reinstate the fuses, not UV light. For PLDs, instead of a conventional notation, crosses are put where wires intersect to indicate fuses being intact. Programmable Gate Array Inverters lead to NAND gates which lead to XOR gates. The XOR inverts. NAND gates and output polarity are programmable. If the polarity of the XOR gate is intact, the NAND gate is shown, otherwise the other input is set to logical 1 and inverted. Programmable Array Logic This is a programmable AND array, but a fixed OR array. In PALs, every output is not programmable with every possible input combination, however they are low cost and easily programmed. If you have any unused AND gates in the array, all fuses must be intact, which sets the output to 0 which doesn't interfere with the OR. Some PALs have tristate buffers for bus driving (the tristate selects whether the PAL is an driving or receiving), hence the PAL can be used for inputs and outputs. Programmable Logic Array This has a programmable AND array and OR array. PLDs have extra security to allow the device to be checked and allows the fuse arrays to be read. Some PLDs have security fuses to stop the devices being read. IDD is continued straight through into DAD.