Hardware Description Languages: An Overview of Verilog and VHDL, Study notes of Computer Architecture and Organization

Download Hardware Description Languages: An Overview of Verilog and VHDL and more Study notes Computer Architecture and Organization in PDF only on Docsity! Lecture 4 Appendix B Hardware Description Languages Study section B.5 page B-26 through B-31. Study and/or read section B.4 as directed in the following notes. Section B.4 Verilog and VHDL are the two most common HDLs. We will study Verilog in this course. We will not become experts, a beginning knowledge of Verilog is all that we want at this time. HDLs may be simulated or synthesized automatically. (Compiled) Two primary data types: wire ## Specifies a combinational signal reg ## Holds a value—ie memory, or a cpu register or … Syntax: wire[31:0] ## Declares a wire that has 32 bits. reg[31:0] ## Declares a reg that has 32 bits. Arrays of registers: reg[31:0] R[0:31] ## Declares an array R of 32 bit reg. Then R[5] would refer to register number 5. Values (of bits): 0, or 1 ## usual meaning F,T, two valued logic z ## value unknown z ## tristate gate values—beyond this course. Now we are back in the study mode, you are expected to comprehend the next figure in detail. It describes a half-adder that you have seen before in our notes or in Section B.5. (Note <= is the non blocking form of an assignment statement. We will not study blocking and non blocking at this time, so for us it will just be an assignment statement.) You should be able to read the above and interpret it in terms of the ALU design work we have done previously in our notes (section B.5). What is missing in this module? Carryout anyone?