Lecture Slides for Introduction to CMOS Circuits | ECE 1192, Study notes of Electrical and Electronics Engineering

Download Lecture Slides for Introduction to CMOS Circuits | ECE 1192 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! 1 Introduction to CMOS VLSI Design Lecture 1: Intro to CMOS Circuits David Harris Harvey Mudd College Spring 2004 Steven Levitan Fall 2008 2 1: Circuits & Layout Slide 2CMOS VLSI Design Outline A Brief History CMOS Gate Design Pass Transistors CMOS Latches & Flip-Flops Standard Cell Layouts Stick Diagrams 5 1: Circuits & Layout Slide 5CMOS VLSI Design Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable 1947: first point contact transistor – John Bardeen and Walter Brattain at Bell Labs – Read Crystal Fire by Riordan, Hoddeson 6 1: Circuits & Layout Slide 6CMOS VLSI Design Transistor Types Bipolar transistors – npn or pnp silicon structure – Small current into very thin base layer controls large currents between emitter and collector – Base currents limit integration density Metal Oxide Semiconductor Field Effect Transistors – nMOS and pMOS MOSFETS – Voltage applied to insulated gate controls current between source and drain – Low power allows very high integration 7 1: Circuits & Layout Slide 7CMOS VLSI Design 1970’s processes usually had only nMOS transistors – Inexpensive, but consume power while idle 1980s-present: CMOS processes for low idle power MOS Integrated Circuits Intel 1101 256-bit SRAM Intel 4004 4-bit μProc 10 EE141 10 © Digital Integrated Circuits2nd Manufacturing MOS transistors Types and Symbols D S G D S G G S D D S G NMOS Enhancement NMOS PMOS Depletion Enhancement B NMOS with Bulk Contact ital Integrated Circuits © Prentice Hall 1995IntroductionECE 1192 © 2006, Steven Levita , University of Pittsburgh Do not forget: These are all 4 terminal devices 11 EE141 11 © Digital Integrated Circuits2nd Manufacturing The Basic Idea… Voltage on the Gate controls the current through the source/drain path N-Channel - N-Switches are ON when the Gate is HIGH and OFF when the Gate is LOW P-Channel - P-Switches are OFF when the Gate is HIGH and ON when the Gate is LOW (ON == Circuit between Source and Drain) ECE 1192 © 2006, Steven Levitan, University of Pittsburgh 12 EE141 12 © Digital Integrated Circuits2nd Manufacturing Transistors as Switches G S D G D S N Switch P Switch 0 1 1 0 Passes “good zeros” Passes “good ones” ECE 1192 © 2006, Steven Levitan, University of Pittsburgh 15 EE141 15 © Digital Integrated Circuits2nd Manufacturing 3D Perspective Polysilicon Aluminum 16 EE141 16 © Digital Integrated Circuits2nd Manufacturing A Modern Dual Well CMOS Process p-well n-well p+ p-epi SiO2 AlCu poly n+ SiO2 p+ gate-oxide Tungsten TiSi2 Dual-Well Trench-Isolated CMOS Process epi – epitaxial = grown with matching crystal structure TiSi – silicide = low resistance coating (real trenches are much deeper) 17 1: Circuits & Layout Slide 17CMOS VLSI Design Complementary CMOS Complementary CMOS logic gates – nMOS pull-down network – pMOS pull-up network – a.k.a. static CMOS pMOS pull-up network output inputs nMOS pull-down network X (crowbar)0Pull-down ON 1Z (float)Pull-down OFF Pull-up ONPull-up OFF 20 1: Circuits & Layout Slide 20CMOS VLSI Design CMOS Gate Design Activity: – Sketch a 4-input CMOS NAND gate 21 1: Circuits & Layout Slide 21CMOS VLSI Design CMOS Gate Design Activity: – Sketch a 4-input CMOS NOR gate A B C D Y 22 1: Circuits & Layout Slide 22CMOS VLSI Design Compound Gates Compound gates can do any inverting function Ex: (AND-AND-OR-INVERT, AOI22)Y A B C D= + A B C D A B C D A B C D A B C D B D Y A C A C A B C D B D Y (a) (c) (e) (b) (d) (f) 25 1: Circuits & Layout Slide 25CMOS VLSI Design Signal Strength Strength of signal – How close it approximates ideal voltage source VDD and GND rails are strongest 1 and 0 nMOS pass strong 0 – But degraded or weak 1 pMOS pass strong 1 – But degraded or weak 0 Thus nMOS are best for pull-down network 26 1: Circuits & Layout Slide 26CMOS VLSI Design Pass Transistors Transistors can be used as switches g s d g s d 27 1: Circuits & Layout Slide 27CMOS VLSI Design Pass Transistors Transistors can be used as switches g s d g = 0 s d g = 1 s d 0 strong 0 Input Output 1 degraded 1 g s d g = 0 s d g = 1 s d 0 degraded 0 Input Output strong 1 g = 1 g = 1 g = 0 g = 0 30 1: Circuits & Layout Slide 30CMOS VLSI Design Tristates Tristate buffer produces Z when not enabled 11 01 10 00 YAEN A Y EN A Y EN EN 31 1: Circuits & Layout Slide 31CMOS VLSI Design Tristates Tristate buffer produces Z when not enabled 111 001 Z10 Z00 YAEN A Y EN A Y EN EN 32 1: Circuits & Layout Slide 32CMOS VLSI Design Nonrestoring Tristate Transmission gate acts as tristate buffer – Only two transistors – But nonrestoring • Noise on A is passed on to Y A Y EN EN 35 1: Circuits & Layout Slide 35CMOS VLSI Design Multiplexers 2:1 multiplexer chooses between two inputs X11 X01 1X0 0X0 YD0D1S 0 1 S D0 D1 Y 36 1: Circuits & Layout Slide 36CMOS VLSI Design Multiplexers 2:1 multiplexer chooses between two inputs 1X11 0X01 11X0 00X0 YD0D1S 0 1 S D0 D1 Y 37 1: Circuits & Layout Slide 37CMOS VLSI Design Gate-Level Mux Design How many transistors are needed? 1 0 (too many transistors)Y SD SD= + 40 1: Circuits & Layout Slide 40CMOS VLSI Design Transmission Gate Mux Nonrestoring mux uses two transmission gates – Only 4 transistors S S D0 D1 YS 41 1: Circuits & Layout Slide 41CMOS VLSI Design Inverting Mux Inverting multiplexer – Use compound AOI22 – Or pair of tristate inverters – Essentially the same thing Noninverting multiplexer adds an inverter S D0 D1 Y S D0 D1 Y 0 1 S Y D0 D1 S S S S S S 42 1: Circuits & Layout Slide 42CMOS VLSI Design 4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects 45 1: Circuits & Layout Slide 45CMOS VLSI Design D Latch Design Multiplexer chooses D or old Q 1 0 D CLK Q CLK CLKCLK CLK DQ Q Q 46 1: Circuits & Layout Slide 46CMOS VLSI Design D Latch Operation CLK = 1 D Q Q CLK = 0 D Q Q D CLK Q 47 1: Circuits & Layout Slide 47CMOS VLSI Design D Flip-flop When CLK rises, D is copied to Q At all other times, Q holds its value a.k.a. positive edge-triggered flip-flop, master-slave flip-flop Fl op CLK D Q D CLK Q 50 1: Circuits & Layout Slide 50CMOS VLSI Design Race Condition Back-to-back flops can malfunction from clock skew – Second flip-flop fires late – Sees first flip-flop change and captures its result – Called hold-time failure or race condition CLK1 D Q1Fl op Fl op CLK2 Q2 CLK1 CLK2 Q1 Q2 51 1: Circuits & Layout Slide 51CMOS VLSI Design Nonoverlapping Clocks Nonoverlapping clocks can prevent races – As long as nonoverlap exceeds clock skew We will use them in this class for safe design – Industry manages skew more carefully instead φ1 φ1φ1 φ1 φ2 φ2φ2 φ2 φ2 φ1 QM QD