Bipolar Junction Transistor: Properties, Biasing, and Circuit Analysis - Prof. Aurangzeb K, Study notes of Electrical and Electronics Engineering

Download Bipolar Junction Transistor: Properties, Biasing, and Circuit Analysis - Prof. Aurangzeb K and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! 1 Chapter # 5 Bipolar Junction Transistor Bipolar Transistor A Bipolar Transistor essentially consists of a pair of PN Junction Diodes that are joined back-to- back. This forms a sort of a sandwich where one kind of semiconductor is placed in between two others. There are two kinds of Bipolar sandwich, the NPNand PNP varieties. The three layers of the sandwich are conventionally called the Collector, Base, and Emitter. The reasons for these names will become clear later once we see how the transistor works. Some of the basic properties exhibited by a Bipolar Transistor are immediately recognizable as being diode-like. However, when the 'filling‘ of the sandwich is fairly thin some interesting effects become possible that allow us to use the Transistor as an amplifier or a switch Bipolar device Unipolar device Bipolar Junction Transistor Bipolar Junction Transistor @ Two-junction device @ Voltage between 2 terminals BJT Junction @ Emitter junction and collector junction. Figure 1 shows the energy levels in an NBN transistor when we aren't externally applying any voltages. We can see that the arrangement looks like a back-to-back pair of PN Diode Junctions wih a thin P-type filing jetween two N-type slices of ‘bread’. In each of the N-type layers ‘conduction can take place by the free movernent of electrons int the conduction band. in the P-type (tiling) layer conduction can take place by the movement of the free holes in the valence band. However, In the absence of any externally applied electtic field, we find that depletion zones form at both PN-Junctions, so no charge wants to move from one layer to another. Fig HPN fipotar Traninter |The Impurity doping concentration in the three regions are substantially ldifferent. Typical doping concentration in the emitter, base and collector are he on the order of 10'2, 10*7, and 10'S /em®, respectively. 2 controls current through the 3rd Emitter Collector Emitter Collector terminal Junction dunction Junction dunetion @ Two possibilities, pnp and npn Emitter Collector Emitter Callector ” Emitter Collector Emitter collector Base Base Base Base NPN Bipolar transistor ph Transistor Forward Active Mode © 4 possible operation modes © Ore important possibility — forward active mode ‘ Enitter-base junction forward biased 4 Base-collector junction reverse biased npn Forward Active Mode Fervor he spite 5 Example 3.1 p119 Calculate the collector and emitter currents, given the base current and current gain. Assume a common-emitter current gain β = 150 and a base current of iB = 15 µA. Also assume that the transistor is biased in the forward-active mode. mA25.2Aµ15150 =×== BFC ii β mA27.2µA15151)1( =×=+= BFE ii β 9934.0 1501 150 1 = + = + = F F F β βα 6 The large value of VCE decreases the effective base width W. Since IS is inversely propositional to W, which cause increase in IC. 7 For a given VBE, if VCE increases, the reverse-biased voltage on the CB junction increase CB depletion region increase Reduces neutral base width Increase minority carrier gradient Increase diffusion current through the base Therefore, iC increase as VCE increase Bipolar Junction Transistors Early voltage Active mode vBE1 vBE2 vBE3 vBE4 Bipolar Junction Transistors Increasing collect voltage VCE causes a decrease in effective base width Resulting in increased iC Early voltage Early voltage VA Since iC is inversely propositional to W, which cause increase in iC . Bipolar Junction Transistors Early voltage .0 1 constvCE C BE v i r = ∂ ∂ = Output resistance r0 CQ EarlyA I V r ,0 ≅ Quiescent collector current Output resistance r0 significantly affect the amplifier characteristics. Active mode vBE1 vBE2 vBE3 vBE4 Slope = 1/r0 R0 = output resistance V30050 , << EarlyAV         +⋅= EarlyA CEVv SFC V veIi TBE , 1α for npn As the collector-Emitter voltage VCE increases, the effective base width decreases. The effect is loss of transistor action !!! Bipolar Junction Transistors Punch-through At punch-through, the two depletion regions meet, and the emitter electrons are swept directly into the collector. 10 Operation Regions of Bipolar Transistors Reverse-Active Region (Poor Amplifier) Cutoff Region (Open Switch) Reverse Bias Saturation Region (Closed Switch) Forward-Active Region (Good Amplifier) Forward Bias Forward BiasReverse Bias Base-Collector JunctionBase-Emitter Junction Binary Logic States For each of the transistors in figures, indicate the mode of operation (forward active, cutoff, saturation, etc.) Example 4.9 V 4.1V 4.8V 9 V 5.0V 9 V 0.2 V • This is an n-p-n transistor. • The collector voltage is higher than the base voltage so the CB junction is reverse biased. • The base voltage is higher than the emitter voltage so that junction is forward biased. • Thus this transistor operates in forward active mode. • This is an n-p-n transistor. • The EB junction is forward biased by 0.2 V, which is not enough to turn it on. • The CB junction is reverse biased. • Thus this transistor is in cutoff mode. 11 Bipolar transistor as an inverter • Transistor in digital logic pass quickly from the off region to the saturation region. Input Output 1(high Vin) 0(low input) 0 1 Digital Logic: Bipolar NOR logic gate Example 3.11 Determine current and voltage in the circuit 3.43(b) Rc=1KΩ RB=20KΩ VBE(on)=0.7V VCE(sat)=0.2V β=50 Lecture #3 Biasing for BJT • Goal of biasing is to establish known Q-point which in turn establishes initial operating region of the transistor. • For a BJT, the Q-point is represented by (IC, VCE) for an npn transistor or (IC, VEC) for a pnp transistor. • The Q-point controls values of diffusion capacitance, transconductance, input and output resistances. • In general, during circuit analysis, we use simplified mathematical relationships derived for a specified operation region, and the Early voltage is assumed to be infinite. • Two practical biasing circuits used for a BJT are: – Four-Resistor Bias network – Two-Resistor Bias network The process by which the quiescent output voltage is caused to fall somewhere the cutoff and saturated values is referred to as biasing. 12 Example 3.13 Q-point has shifted Substantially. Q-point is not stabilized Against the variation β. 15 Example 3.14 p141 Bipolar Transistor Biasing Voltage-Divider Biasing and Bias Stability Voltage-Divider Biasing and Bias Stability Bipolar Transistor Biasing The design requirement for Bias Stability ETH RR )1( β+<< ETH BETH BQCQ RR onVVII )1( ))(( β ββ ++ + == ETH BETH BQ RR onVVI )1( )( β++ + = E BETH BQCQ R onVVII )1( ))(( β ββ + + ≅= Normally β >>1 ; therefore β/(1+β) ≈1. E BETH CQ R onVVI )(+≅ Q-point is stabilized against β variation. However, if RTH is too small, then R1 and R2 are small, and excessive power is dissipated in these resistors. The general rule that a circuit is considered bias stable when, ETH RR )1(1.0 β+≅ Four Resistor Bias Circuit Example A 2N2222A is connected as shown with R1 = 6.8 kΩ, R2 = 1 kΩ, RC = 3.3 kΩ, RE = 1 kΩ, , VCC = 30 V, VBE(on) = 0.7 V. Compute VCEQ for β=100 and 300. (1) β = 100 V RR RVccVV THB 85.318.6 130 21 2 = + ⋅ = + == Ω= + ⋅ = + == k RR RRRR THB 872.018.6 18.6 21 21 A RR VVI ETH BETH B µβ 92.30 1101872.0 7.085.3 )1( = ⋅+ − = ++ − = ICQ = β IB = 3.09 mA IEQ = (1+ β )IB = 3.12 mA VCEQ = VCC-ICRC-IERE = 30-3.09×3.3-3.12×1=16.68V (2) β = 300 V85.3 18.6 130 21 2 = + ⋅ = + == RR RVVV CCTHB kΩ872.018.6 18.6 21 21 = + ⋅ = + == RR RRRR THB µA43.10 1301872.0 7.085.3 )1( = ⋅+ − = ++ − = ETH BETH B RR VVI β ICQ = 300 IB = 3.13 mA IEQ = (1+ β )IB = 3.14 mA VCEQ = VCC-ICRC-IERE = 30-3.13×3.3-3.14×1=16.53V 16 “The above table shows that even with wide variation of β the bias points are very stable”. β = 100 β = 300 % Change VCEQ 16.68 V 16.53 V 0.9 % ICQ 3.09 mA 3.13 mA 1.29 % Example A 2N2222A is connected as shown with R1 = 6.8 kΩ, R2 = 1 kΩ, RC = 3.3 kΩ, RE = 1 kΩ, , VCC = 30 V, VBE(on) = 0.7 V. Compute VCEQ for β=100 and 300. Four Resistor Bias Circuit Voltage-Divider Biasing and Bias Stability Bipolar Transistor Biasing BJT Thermal Runaway Without RE RE stabilizes Q-point with respect to temperature. Example 3.15 VBE(on) ⋅⋅⋅⋅⋅⋅⋅⋅⋅(3.37) Example 3.15 Now From Thevenin theorem 17 Resistor Tolerances Voltage-Divider Biasing and Bias Stability Bipolar Transistor Biasing Find worst-case values of IC and VCE β = 75 with 50% tolerance, VA = 50 V, 5 % tolerance on VCC , 10% tolerance for each resistor. Bipolar Transistor Biasing Example for the worst-case analysis Analysis: Resistor Tolerances E BEEQ EC R VV II − =≅ Extremes of RE : 14.4 kΩ and 17.6 kΩ (10% tolerance) . 21 1 RR R VV CCEQ + = To maximize VEQ , VCC and R1 should be maximized, R2 should be minimized and opposite for minimizing VEQ . Extremes of VEQ : 4.78 V and 3.31 V. Using these values, extremes for IC : 283µA and 148µA. BEEQCCCCCEE E BEEQ CCCCEECCCCCE VVIRVVRR VV IRVIRIRVV +−−≅ − −−≅−−= → To maximize VCE , IC and RC should be minimized, and opposite for minimizing VEQ . Extremes of VCE : 7.06 V (forward-active region) and 0.471 V To maximize IC , VEQ should be maximized, RE should be minimized and opposite for minimizing IC. Multistage Circuit Bipolar Transistor Biasing Most transistor circuit contains more than one transistor We can analyze and design these multistage circuits in much the same way as single transistor circuit.