Bipolar Junction Transistor: Properties, Operation, and Biasing - Prof. Aurangzeb Khan, Study notes of Electrical and Electronics Engineering

Download Bipolar Junction Transistor: Properties, Operation, and Biasing - Prof. Aurangzeb Khan and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! HW #1 je a Ga = 10-416 = 10") 9.30 am) =U 8 88) tenern if) eon( Fath ona s tian 442A voltage epulator comnts of 68 Zeer dade sre with 2008 resistor and a 9 power sappy. (a) Negi cleat the diode cent and power Ipzuima 1 SH x 100 = 1308 Fa = 2868) — 17 WW 116.8 = a Chapter # 3 Bipolar Junction Transistor Bipolar Junction Transistor @ Has 3 separately doped regions and 2 pn Junctions @ With 2 junctions, transistor ‘© Has 4 possible cperetion modes # Depends on bias conditions for ecch unerion © Hos interactions between junctions © Bipolar — transistor current volves beth electrons and holes 2 Bipolar Transistor A Bipolar Transistor essentially consists of a pair of PN Junction Diodes that are joined back-to- back. This forms a sort of a sandwich where one kind of semiconductor is placed in between two others. There are two kinds of Bipolar sandwich, the NPNand PNP varieties. The three layers of the sandwich are conventionally called the Collector, Base, and Emitter. The reasons for these names will become clear later once we see how the transistor works. Some of the basic properties exhibited by a Bipolar Transistor are immediately recognizable as being diode-like. However, when the 'filling‘ of the sandwich is fairly thin some interesting effects become possible that allow us to use the Transistor as an amplifier or a switch Base-collector junction at reverse bias NPN Recombination current in the base • Some of the free electrons crossing the base encounter a hole and ‘drop into it’. As a result the base region loses one of its positive charges (holes) each time this happens. • For particle BJP only about 1% of the free electrons which try to cross base region get caught in this way. Hence we see a base current, IB, which is typically around one hundred times smaller than the emitter current, IE. 5 Operation Regions of Bipolar Transistors Reverse-Active Region (Poor Amplifier) Cutoff Region (Open Switch) Reverse Bias Saturation Region (Closed Switch) Forward-Active Region (Good Amplifier) Forward Bias Forward BiasReverse Bias Base-Collector JunctionBase-Emitter Junction Binary Logic States Bipolar transistor as an inverter • Transistor in digital logic pass quickly from the off region to the saturation region. Input Output 1(high Vin) 0(low input) 0 1 Digital Logic: Bipolar NOR logic gate Example 3.11 Determine current and voltage in the circuit 3.43(b) Rc=1KΩ RB=20KΩ VBE(on)=0.7V VCE(sat)=0.2V β=50 Lecture #3 Biasing for BJT • Goal of biasing is to establish known Q-point which in turn establishes initial operating region of the transistor. • For a BJT, the Q-point is represented by (IC, VCE) for an npn transistor or (IC, VEC) for a pnp transistor. • The Q-point controls values of diffusion capacitance, transconductance, input and output resistances. • In general, during circuit analysis, we use simplified mathematical relationships derived for a specified operation region, and the Early voltage is assumed to be infinite. • Two practical biasing circuits used for a BJT are: – Four-Resistor Bias network – Two-Resistor Bias network The process by which the quiescent output voltage is caused to fall somewhere the cutoff and saturated values is referred to as biasing. 6 Example 3.13 Q-point has shifted Substantially. Q-point is not stabilized Against the variation β. 7 Tolerances - Worst-Case Analysis: Example • Problem: Find worst-case values of IC and VCE. • Given data: βFO = 75 with 50% tolerance, VA = 50 V, 5 % tolerance on VCC , 10% tolerance for each resistor. • Analysis: IC ≅ IE = V EQ − V BE R E To maximize IC , VEQ should be maximized, RE should be minimized and opposite for minimizing IC. Extremes of RE are: 14.4 kΩ and 17.6 kΩ. V EQ = VCC R 1 R 1 + R 2 To maximize VEQ, VCC and R1 should be maximized, R2 should be minimized and opposite for minimizing VEQ. Tolerances - Worst-Case Analysis: Example (cont.) Extremes of VEQ are: 4.78 V and 3.31 V. Using these values, extremes for IC are: 283 µA and 148 µA. To maximize VCE , IC and RC should be minimized, and opposite for minimizing VEQ. Extremes of VCE are: 7.06 V (forward-active region) and 0.471 V (saturated, hence calculated values for VCE and IC actually not correct). V CE = V CC − RC IC − R E IE ≅ VCC − RC IC − V EQ − V BE R E R E ∴ VCE ≅ VCC − RC IC − V EQ + V BE BJT SPICE Model • Besides capacitances associated with the physical structure, additional components are: diode current iS and substrate capacitance CJS related to the large area pn junction that isolates the collector from the substrate and one transistor from the next. • RB is resistance between external base contact and intrinsic base region. • Collector current must pass through RC on its way to active region of collector- base junction. • RE models any extrinsic emitter resistance in device. BJT SPICE Model Typical Values Saturation Current IS = 3x10-17 A Forward current gain BF = 100 Reverse current gain BR = 0.5 Forward Early voltage VAF = 75 V Base resistance RB = 250 Ω Collector Resistance RC = 50 Ω Emitter Resistance RE = 1 Ω Forward transit time TT = 0.15 ns Reverse transit time TR = 15 ns