Download Biasing Techniques for BJT Transistors: Q-Point Determination and Worst-Case Analysis - Pr and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! 1 Biasing for BJT • Goal of biasing is to establish known Q-point which in turn establishes initial operating region of the transistor. • For a BJT, the Q-point is represented by (IC, VCE) for an npn transistor or (IC, VEC) for a pnp transistor. • The Q-point controls values of diffusion capacitance, transconductance, input and output resistances. • In general, during circuit analysis, we use simplified mathematical relationships derived for a specified operation region, and the Early voltage is assumed to be infinite. • Two practical biasing circuits used for a BJT are: – Four-Resistor Bias network – Two-Resistor Bias network The process by which the quiescent output voltage is caused to fall somewhere the cutoff and saturated values is referred to as biasing. 2 Example 3.13 Q-point has shifted Substantially. Q-point is not stabilized Against the variation β. 5 Tolerances - Worst-Case Analysis: Example • Problem: Find worst-case values of IC and VCE. • Given data: βFO = 75 with 50% tolerance, VA = 50 V, 5 % tolerance on VCC , 10% tolerance for each resistor. • Analysis: IC ≅ IE = V EQ − V BE R E To maximize IC , VEQ should be maximized, RE should be minimized and opposite for minimizing IC. Extremes of RE are: 14.4 kΩ and 17.6 kΩ. V EQ = VCC R 1 R 1 + R 2 To maximize VEQ, VCC and R1 should be maximized, R2 should be minimized and opposite for minimizing VEQ. Tolerances - Worst-Case Analysis: Example (cont.) Extremes of VEQ are: 4.78 V and 3.31 V. Using these values, extremes for IC are: 283 µA and 148 µA. To maximize VCE , IC and RC should be minimized, and opposite for minimizing VEQ. Extremes of VCE are: 7.06 V (forward-active region) and 0.471 V (saturated, hence calculated values for VCE and IC actually not correct). VCE = VCC − RC IC − RE I E ≅ VCC − RC IC − V EQ − V BE R E RE ∴ VCE ≅ VCC − RC IC − V EQ + V BE 6 BJT SPICE Model • Besides capacitances associated with the physical structure, additional components are: diode current iS and substrate capacitance CJS related to the large area pn junction that isolates the collector from the substrate and one transistor from the next. • RB is resistance between external base contact and intrinsic base region. • Collector current must pass through RC on its way to active region of collector- base junction. • RE models any extrinsic emitter resistance in device. BJT SPICE Model Typical Values Saturation Current IS = 3x10-17 A Forward current gain BF = 100 Reverse current gain BR = 0.5 Forward Early voltage VAF = 75 V Base resistance RB = 250 Ω Collector Resistance RC = 50 Ω Emitter Resistance RE = 1 Ω Forward transit time TT = 0.15 ns Reverse transit time TR = 15 ns Chap 5 - 22
