Lecture Slides on Combinational MOS Logic Circuits Design Approaches | EE 534, Study notes of Electrical and Electronics Engineering

Download Lecture Slides on Combinational MOS Logic Circuits Design Approaches | EE 534 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! EE 534 fall 2003 University of South Alabama EE534 VLSI Design System Fall 2003 Lecture 17:Chapter 7 Combinational MOS logic circuits design approaches EE 534 fall 2003 University of South Alabama Review: Load Lines of Ratioed Gates 0.0 1.0 2.0 3.0 4.0 5.0 Vout (V) 0 0.25 0.5 0.75 1 I L (N or m al iz ed ) Resistive load Pseudo-NMOS Depletion load Current source EE 534 fall 2003 University of South Alabama CMOS Transmission Gate A CMOAS transmission gate can be constructed by parallel combination of NMOS and PMOS transistors, with complementary gate signals. The main advantage of the CMOS transmission gate compared to NMOS transmission gate is to allow the input signal to be transmitted to the output without the threshold voltage attenuation. CMOS transmission gate EE 534 fall 2003 University of South Alabama Characteristics of a CMOS Transmission gate Case I: If φ =VDD, , VI=VDD, and VO is initially zero. In NMOS transistor, under above Condition, terminal ‘a’ acts as the drain and terminal ‘b’ acts as the source. For the PMOS, device terminal ‘c’ acts as the drain and terminal ‘d’ acts as the source. In order to charge the load capacitor, current enters the NMOS drain and the PMOS source. The NMOS gate to source voltage is, VGSN = φ - VO = VDD - VO this implies that VGSN continuously change. And for PMOS source-to-gate voltage is VGSP = VI - φ = VDD – 0 = VDD This implies that VGSP remains constant. Drain source source Drain 0=φ Charging path EE 534 fall 2003 University of South Alabama Characteristics of a CMOS Transmission gate (Cont.) When VO=VDD-VTN, VGSN=VTN, the NMOS transmission gate cuts off and IDN=0. However, PMOS transistor continue to conduct, because VGSP of the PMOS is a constant (VGSP=VDD). In PMOS transistor IDP=0, when VSDP=0, which would be possible only, if, VO = VI = 5V Drain source source Drain NMOS transmission gate This implies that a logic ‘1’ is transmitted unattenuated through the CMOS transmission gate in contrast to the NMOS transmission gate. EE 534 fall 2003 University of South Alabama Characteristics of a CMOS Transmission gate (Cont.) Case II: If VI = 0, φ = VDD, VO=VDD initially. terminal ‘a’ acts as a source and terminal ‘b’ acts as a drain. For the PMOS transistor terminal ‘c’ acts as a source and terminal ‘d’ acts as a drain. In order to discharge the capacitors current enter the NMOS drain and PMOS source. The NMOS gate to source voltage is, And PMOS source to gate voltage is When VSGP=VO=|VTP|, PMOS transistor cutoff and iDP=o However, since VGSN=VDD, the NMOS transistor continue conducting and capacitor completely discharge to zero. Finally, VO=0, which is a good logic 0. source drain sourcedrain OOOSGP vvvv =−=−= 0φ DDDDIGSN Vvvv =−=−= 0φ 0=φ discharging path EE 534 fall 2003 University of South Alabama Equivalent Resistance Model For a rising transition at the output (step input) NMOS sat, PMOS sat until output reaches |VTP| NMOS sat, PMOS lin until output reaches VDD-VTN NMOS off, PMOS lin for the final VDD – VTN to VDD voltage swing Drain source source Drain Vin Vout Vcc 0V nDS outDD neq I VVR , , − = pDS outDD peq I VVR , , − = EE 534 fall 2003 University of South Alabama Equivalent Resistance – Region 1 NMOS sat: PMOS sat: ( ) ( )221 , tnoutDDn outDD neq VVVk VVR −− − = ( ) ( )221, tpDDp outDD peq VVk VVR −− − = Drain source source Drain NMOS sat, PMOS sat until output reaches |VTP| because drain to source voltage is still high EE 534 fall 2003 University of South Alabama Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors EE 534 fall 2003 University of South Alabama Static vs Dynamic Storage Static storage preserve state as long as the power is on have positive feedback (regeneration) with an internal connection between the output and the input useful when updates are infrequent (clock gating) Dynamic storage store state on parasitic capacitors only hold state for short periods of time (milliseconds) require periodic refresh usually simpler, so higher speed and lower power EE 534 fall 2003 University of South Alabama Dynamic CMOS Advantages: Faster – why? - Reduced input load - No switching contention Less layout area Disadvantages: Charge leakage Charge sharing Capacitive coupling Cannot be cascaded Complicated timing/clocking Higher power Lower noise margins Gnd NMOS network clk clk These issues are discussed in chapter 9 EE 534 fall 2003 University of South Alabama TG Applications: Multiplexer (MUX) circuit Case I: When the input S is logic high Bottom transistor is conducting and output is equal to input B Case II: When the input S is logic low Bottom Tg turn off and top TG turn on and output is equal to input A EE 534 fall 2003 University of South Alabama TG Multiplexer GND VDD In1 In2S S S S S S S In2 In1 F F F = !(In1 • S + In2 • S) EE 534 fall 2003 University of South Alabama Transmission Gate XOR A B F B A B B M1 M2 M3/M4 B A F 1 0 1 0 1 1 1 1 0 EE 534 fall 2003 University of South Alabama Example: Full Adder VDD VDD VDD VDD A B Ci S Co X B A Ci A BBA Ci A B Ci Ci B A Ci A B BA Co = AB + Ci(A+B) 28 transistors Carry is the critical signal: closest to the output EE 534 fall 2003 University of South Alabama A Revised Adder Circuit: applying the design techniques to reduce area and delay VDD Ci A BBA B A A B Kill Generate"1"-Propagate "0"-Propagate VDD Ci A B Ci Ci B A Ci A BBA VDD SCo 24 transistors EE 534 fall 2003 University of South Alabama TG Full Adder Sum Cout A B Cin EE 534 fall 2003 University of South Alabama Transmission Gate Full Adder A B P Ci VDD A A A VDD Ci A P AB VDD VDD Ci Ci Co S Ci P P P P P Sum Generation Carry Generation Setup Similar delays for sum and carry