Lecture Slides on Internal Memory Details - Computer Architecture | CSCI 4717, Study notes of Computer Architecture and Organization

Download Lecture Slides on Internal Memory Details - Computer Architecture | CSCI 4717 and more Study notes Computer Architecture and Organization in PDF only on Docsity! 1 Memory Details – Page 1 of 34CSCI 4717 – Computer Architecture CSCI 4717/5717 Computer Architecture Topic: Internal Memory Details Reading: Stallings, Sections 5.1 & 5.3 Memory Details – Page 2 of 34CSCI 4717 – Computer Architecture Basic Organization Memory Cell Operation • Represent two stable/semi-stable states representing 1 and 0 • Capable of being written to at least once • Capable of being read multiple times Memory Details – Page 3 of 34CSCI 4717 – Computer Architecture Semiconductor Memory Types • Random Access Memory (RAM) • Read Only Memory (ROM) • Programmable Read Only Memory (PROM) • Eraseable Programmable Read Only Memory (EPROM) • Electronically Eraseable Programmable Read Only Memory (EEPROM) • Flash Memory Memory Details – Page 4 of 34CSCI 4717 – Computer Architecture Random Access Memory • Misnomer (Last week we learned that the term Random Access Memory refers to accessing individual memory locations directly by address) • RAM allows reading and writing (electrically) of data at the byte level • Two types – Static RAM – Dynamic RAM • Volatile Memory Details – Page 5 of 34CSCI 4717 – Computer Architecture Read Only Memory (ROM) • Sometimes can be erased for reprogramming, but might have odd requirements such as UV light or erasure only at the block level • Sometimes require special device to program, i.e., processor can only read, not write • Types – EPROM – EEPROM – Custom Masked ROM – OTPROM – FLASH Memory Details – Page 6 of 34CSCI 4717 – Computer Architecture ROM Uses • Permanent storage – nonvolatile • Microprogramming • Library subroutines • Systems programs (BIOS) • Function tables • Embedded system code 2 Memory Details – Page 7 of 34CSCI 4717 – Computer Architecture EPROM • Written to only with a programmer. • Erased with ultraviolet light • Positive – non-volatile storage without battery – can write to it, but only with aid of programmer • Negative – programmer requirements – Expensive – locations must be erased before writing Memory Details – Page 8 of 34CSCI 4717 – Computer Architecture EEPROM • Written to with either programmer or the processor (electrically) • Erased with either a programmer or the processor (byte-by-byte electrically) • Positive – non-volatile memory without batteries – programmable a single-location at a time • Negative – Expensive – only smaller sizes available – extremely slow write times (10 mS vs. 100 to 200 nS) Memory Details – Page 9 of 34CSCI 4717 – Computer Architecture Custom masked ROM • You send the ROM manufacturer your data and they mask it directly to the ROM • Use only when you are selling large volume of a single product • Positive – becomes cheaper to use for approximately more than 2000 parts – components come from chip manufacturer already programmed and tested taking out a manufacturing step • Negative – costs several thousand dollars for custom mask – software changes are costly – cannot be reprogrammed Memory Details – Page 10 of 34CSCI 4717 – Computer Architecture OTPROM • Uses fuses that are burned to disconnect a logic 1 and turn it to a logic 0. • Written to by you using a programmer similar to EPROM • Once it's written to, the data is in there forever. • Positive – cheaper than EPROM due to cheaper packaging – more packaging options than EPROM due to less constraints like erasure window – standard "off-the-shelf" component – cheaper than Custom masked ROM up to about 10,000 devices • Negative – to reprogram, have to throw out the chip - Should only be used for stable design Memory Details – Page 11 of 34CSCI 4717 – Computer Architecture FLASH • These memories are basically EEPROMs except that erasure occurs at the block level in order to speed up the write process • Non-volatile • This makes FLASH work like a fast, solid state hard drive • Positive – non-volatile – higher densities than both SRAM and DRAM • Negative – process of storing data is at a block level (and slower) – data cell must be erased before writing data to it Memory Details – Page 12 of 34CSCI 4717 – Computer Architecture Flash Density Comparison Source: Griffin, J., Matas, B., de Suberbasaux, C., ”Memory 1996” , Integrated Circuit Engineering Corporation, Scottsdale, AZ, on-line: http://smithsonianchips.si.edu/ice/cd/MEM96/TITLE.PDF 5 Memory Details – Page 25 of 34CSCI 4717 – Computer Architecture DRAM Refresh • Two things discharge a DRAM capacitor – Data read – Leakage current • Need refreshing even when powered and idle (once every few milliseconds) • Refresh circuit included on chip – Even with added cost, still cheaper than SRAM cost • Refresh process involves disabling chip, then reading data and writing it back • Performed by counting through “rows” • Takes time – Slows down apparent performance Memory Details – Page 26 of 34CSCI 4717 – Computer Architecture DRAM Organization Example Memory Details – Page 27 of 34CSCI 4717 – Computer Architecture Module Organization: Using multiple memories in parallel to increase data bus width Memory Details – Page 28 of 34CSCI 4717 – Computer Architecture Module Organization: Using chip selects to increase the number of words Memory Details – Page 29 of 34CSCI 4717 – Computer Architecture Advanced DRAM Organization • SRAM Cache was the traditional way to improve performance of the DRAM • Basic DRAM is unchanged since first RAM chips • Enhanced DRAM – Contains small SRAM as well – SRAM acts as cache holding last line read • Cache DRAM (CDRAM) – Larger SRAM added – Acts as either cache or serial buffer Memory Details – Page 30 of 34CSCI 4717 – Computer Architecture FPM and EDO DRAM • Fast Page Mode (FPM) shortens cycle time by allowing processor to use the same row address, but a different column address (removes one step in the addressing sequence) • The data of a single row is referred to as a "page" • Extended Data-Out (EDO) allows the processor to overlap the data read cycle with the write for the next column address • EDO result is a savings of approximately 10 ns for each read within a single page 6 Memory Details – Page 31 of 34CSCI 4717 – Computer Architecture Synchronous DRAM (SDRAM) • Access is synchronized with an external clock • Address is presented to RAM • RAM finds data (CPU waits in conventional DRAM) • Since SDRAM moves data in time with system clock, CPU knows when data will be ready • CPU does not have to wait, it can do something else • Burst mode allows SDRAM to set up stream of data and fire it out in block • DDR-SDRAM sends data twice per clock cycle (leading & trailing edge) Memory Details – Page 32 of 34CSCI 4717 – Computer Architecture SDRAM Sample Timing Memory Details – Page 33 of 34CSCI 4717 – Computer Architecture RAMBUS or RDRAM • Suggests transfer rates from 1.6 to 10.7 GBytes per second. • Subsystem consists of the memory array, the RAM controller, and a well-defined bus • Bus definition includes all components including the microprocessor and any other devices that may use it • Vertical package (all pins on one side) called Rambus in-line memory modules (RIMMs) • Adopted by Intel for Pentium & Itanium Memory Details – Page 34 of 34CSCI 4717 – Computer Architecture Bus definition • Data exchange over 28 wires • Different definitions require bus lengths less than 12 cm long (some definitions are longer up to 25 cm long) • Bus addresses up to 320 RDRAM chips • Communication protocol is packet-based • Implements pipelined operation overlapping command and data • 800 to 1200 MHz operation • Inititial access time = 480ns • After that, 1.6 GBps