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Introduction to VHDL
CLASS MATERIALS
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Very High Speed Integrated Circuit Har dware Description Language • Industry standard language to describe hardware • Originated from work in 70’s & 80’s by the U.S. Departm ent of Defence • Root : ADA Language ► a structured, statically typed, imperative and object-oriented high-level computer programming language based on Pascal • In 1986, VHDL was proposed as an IEEE standard, and in 1987, it was adopted as the IEEE 1076 standard VHDL Format : Library (3) • std_logic_arith : defines some types and basic arithmetic operations for representing integers in standard ways a few functions arithmetic functions : +, -, * comparison functions : <, >, <=, >=, =, /= and etc. Ex. signal u1, u2 : unsigned (3 downto 0); signal s1 : signed (3 downto 0); signal s2 : signed (4 downto 0); • • • signal v2 : std_logic_vector (4 downto 0); u1 <= “1001”; -- = 9 s1 <= “1001”; -- = -7 • • • wait for 10 ns; s2 <= u1 + s1; -- = 2 v2 := u1 + s1; -- = “0010” VHDL Format : Library (4) • std_logic_unsigned : defines all of the same arithmatic (+, -, *), comparison (<, <=, >, >=, =, /=) and shift (shl, shr) operations as the std_logic_arith library. This difference is that the extensions will take std_logic_vector values as arguments and treat them as unsigned integers ↔ std_logic_signed Ex. signal u1, u2 : unsigned (3 downto 0); signal s1 : signed (3 downto 0); signal s2 : signed (4 downto 0); • • • signal v2 : std_logic_vector (4 downto 0); u1 <= “1001”; -- = 9 s1 <= “1001”; -- = -7 • • • 『http://www.cs.sfu.ca/~ggbaker/reference/std_logic/』 VHDL Format : Entity (1) • Specifies the name of entity, the port of the entity and enti ty-related information. Ex 1. ENTITY and2 IS PORT ( a, b : IN BIT; c : OUT BIT ); END and2 A B C VHDL Format : Architecture (2) • f = Ā2A3 + A1 A3 A4 Ex. ARCHITECTURE Logicfunc of func2 IS BEGIN f <= ((NOT A2) AND A3) OR (A1 AND A3 AND A4 ); END Logicfunc ; • f = (Ā3 + A4) (Ā1 + A4) (A1 + Ā2 + A3+ Ā4) Ex. ARCHITECTURE Logicfunc of func2 IS BEGIN f <= ((NOT A3) OR A4) AND ((NOT A1) OR A4 ) AND (A1 OR (NOT A2) OR A3 OR (NOT A4)) ; END Logicfunc
VHDL Format : Architecture (3)
STRUCTURAL DESIGN
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VHDL Format : Architecture (4) • STRUCTURAL DESIGN Ex. ARCHITECTURE netlist of mux IS COMPONENT andgate port ( a, b, c : IN bit; d : OUT bit) ; END COMPONENT ; COMPONENT inverter port ( in1 : IN bit; x : OUT bit) ; END COMPONENT ; COMPONENT orgate port ( a, b, c, d : IN bit; x : OUT bit) ; END COMPONENT SIGNAL s0_inv, s1_inv, x1, x2, x3, x4 : BIT; BEGIN U1 : inverter (s0, s0_inv) ; U2 : inverter (s1, s1_inv) ; U3 : andgate (a, s0_inv, s1_inv, x1) ; U4 : andgate (b, s0, s1_inv, x2) ; U5 : andgate (c, s0_inv, s1, x3) ; U6 : andgate (d, s0, s1, x4) ; U7 : orgate (x2 => b, x1 => a, x4 => d, x3 => c, x => x) ; END netlist Definition
