Lecture Slides on Inverter Systems | ECEN 4517, Study notes of Electrical and Electronics Engineering

Download Lecture Slides on Inverter Systems | ECEN 4517 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! ECEN 4517 1 Lecture 3 ECEN 4517/5517 Step-up dc-dc converter with isolation (flyback) Feedback controller to regulate HVDC Experiments 3 and 4: inverter system DC-AC inverter (H-bridge) 12 VDC HVDC: 120 - 200 VDC AC load 120 Vrms 60 Hz Battery DC-AC inverter H-bridge DC-DC converter Isolated flyback +– d(t) Feedback controller Vref Digital controller d(t) + vac(t) – ECEN 4517 2 Due dates This week in lab (Jan. 27-29): Nothing due. Finish Exps. 1 and 2. Next week in lecture (Feb. 3): Prelab assignment for Exp. 3 Part 1 (one from every student) Next week in lab (Feb. 3-5): Final reports due for Exps. 1 and 2, at beginning of lab period Do Exp. 3 part 1 ECEN 4517 5 “Modified Sine-Wave” Inverter vac(t) has a rectangular waveform Inverter transistors switch at 60 Hz, T = 8.33 msec T/2 DT/2 + VHVDC – VHVDC vac(t) RMS value of vac(t) is: Vac,RMS = 1 T vac 2 t dt 0 T = D VHVDC • Choose VHVDC larger than desired Vac,RMS • Can regulate value of Vac,RMS by variation of D • Waveform is highly nonsinusoidal, with significant harmonics ECEN 4517 6 PWM Inverter Average vac(t) has a sinusoidal waveform Inverter transistors switch at frequency substantially higher than 60 Hz • Choose VHVDC larger than desired Vac,peak • Can regulate waveshape and value of Vac,RMS by variation of d(t) • Can achieve sinusoidal waveform, with negligible harmonics • Higher switching frequency leads to more switching loss and need to filter high-frequency switching harmonics and common- mode currents t vac(t) ECEN 4517 7 The buck-boost converter Subinterval 1 Subinterval 2 + – + V – Vg iL + – + V – Vg iL + – + V – 1 2 Vg iL V Vg = – D 1 – D Switch in position 1: Vg charges inductor Switch in position 2: energy stored in inductor is transferred to output Conversion ratio: ECEN 4517 10 A simple transformer model Multiple winding transformer Equivalent circuit model n1 : n2 : n3 + v1(t) – + v2(t) – + v3(t) – i1(t) i2(t) i3(t) n1 : n2 : n3 + v1(t) – + v2(t) – + v3(t) – i1(t) i2(t) i3(t) Ideal transformer i1'(t) LM iM(t) v1(t) n1 = v2(t) n2 = v3(t) n3 = ... 0 = n1i1' (t) + n2i2(t) + n3i3(t) + ... ECEN 4517 11 The magnetizing inductance LM Transformer core B-H characteristic• Models magnetization of transformer core material • Appears effectively in parallel with windings • If all secondary windings are disconnected, then primary winding behaves as an inductor, equal to the magnetizing inductance • At dc: magnetizing inductance tends to short-circuit. Transformers cannot pass dc voltages • Transformer saturates when magnetizing current i M is too large B(t) ∝ v1(t) dt H(t) ∝ iM(t) slope ∝ LM saturation ECEN 4517 12 Volt-second balance in LM The magnetizing inductance is a real inductor, obeying integrate: Magnetizing current is determined by integral of the applied winding voltage. The magnetizing current and the winding currents are independent quantities. Volt-second balance applies: in steady-state, i M (T s ) = i M (0), and hence n1 : n2 : n3 + v1(t) – + v2(t) – + v3(t) – i1(t) i2(t) i3(t) Ideal transformer i1'(t) LM iM(t)v1(t) = L M diM(t) dt iM(t) – iM(0) = 1 L M v1(τ)dτ 0 t 0 = 1Ts v1(t)dt 0 Ts ECEN 4517 15 Subinterval 2 CCM: small ripple approximation leads to vL = – v n iC = i n – v R ig = 0 vL = – V n iC = I n – V R ig = 0 + – + v – Vg 1:n C Transformer model i R iC i/n – v/n + + vL – ig = 0 Q1 off, D1 on ECEN 4517 16 CCM Flyback waveforms and solution Volt-second balance: Conversion ratio is Charge balance: Dc component of magnetizing current is Dc component of source current is vL iC ig t Vg 0 DTs D'Ts Ts Q1 D1 Conducting devices: –V/n –V/R I/n – V/R I vL = D Vg + D' – V n = 0 M(D) = VVg = n DD' iC = D – V R + D' I n – V R = 0 I = nVD'R Ig = ig = D I + D' 0 ECEN 4517 17 Equivalent circuit model: CCM Flyback + – + – R + V – Vg D'I n D'V n + – DVgDI IIg + – R + V – Vg IIg 1 : D D' : n vL = D Vg + D' – V n = 0 iC = D – V R + D' I n – V R = 0 Ig = ig = D I + D' 0 ECEN 4517 20 Approach See transformer design procedures (textbook chapters 14 and 15) Select core size and switching frequency Choose turns ratio n2/n1, LM, D, and fs (choose your own values, don t use values in supplementary notes) Select primary turns n1 so that total loss Ptot in flyback transformer is minimized: Ptot = Pfe + Pcu = core loss plus copper loss Determine air gap length Determine primary and secondary wire gauges Make sure that core does not saturate Turn in your design - prelab assignment due next Tuesday ECEN 4517 21 Core loss CCM flyback example dB(t) dt = vM (t) n1Ac dB(t) dt = Vg n1Ac B(t) Hc(t) Minor B–H loop, CCM flyback example B–H loop, large excitation Bsat ΔBBmax vM(t) 0 Vg DTs B(t) Bmax 0 ΔB Vg n1Ac B-H loop for this application: The relevant waveforms: B(t) vs. applied voltage, from Faraday s law: For the first subinterval: Solve for B: B = VgDTs 2n1Ac ECEN 4517 22 Calculation of ac flux density and core loss B = VgDTs 2n1Ac Pfe = K fe(ΔB) β Ac lm = slope Kfe = constant that depends on fs Aclm = core volume Fitting an equation to the plot at right At 60˚C: = 2.6 Kfe = 16 (50 kHz), 40 (100 kHz) with Pfe in watts, Aclm in cm3, B in Tesla More turns less B less core loss From previous slide: ECEN 4517 25 Effect of transformer leakage inductance + – LM + v – Vg Q1 D11:n C Transformer model iig R Ll + vl – + vT(t) – • Leakage inductance L l is caused by imperfect coupling of primary and secondary windings • Leakage inductance is effectively in series with transistor Q1 • When MOSFET switches off, it interrupts the current in L l • L l induces a voltage spike across Q1 t Vg + v/n vT(t) iRon DTs {Voltage spikecaused byleakageinductance vl = L l dil dt If the peak magnitude of the voltage spike exceeds the voltage rating of the MOSFET, then the MOSFET will fail. ECEN 4517 26 Protection of Q1 using a voltage-clamp snubber + – + v – Vg Q1 D11:n C Flyback transformer ig R + vT(t) – CsRs – vs + Snubber{ • Snubber provides a place for current in leakage inductance to flow after Q1 has turned off • Peak transistor voltage is clamped to Vg + vs • vs > V/n • Energy stored in leakage inductance (plus more) is transferred to capacitor Cs, then dissipated in RsUsually, Cs is large Decreasing Rs decreases the peak transistor voltage but increases the snubber power loss See supplementary flyback notes for an example of estimating Cs and Rs ECEN 4517 27 Reminders on Exp. 2 (this week’s experiment) Layout issues! – Must use bypass capacitors on power supplies – Place ceramic capacitor across power supply and ground pins of every IC – Especially place ceramic bypass capacitor as close as possible to power and ground pins of gate driver IC – Place bypass capacitor on your board across power and ground terminals that supply power to the MOSFET and power resistor Capturing oscilloscope waveforms – Capture screen shots of oscilloscope waveforms, for inclusion in final report – Can use floppy disk, or (on several of the lab scopes) can use ethernet cable and enter scope IP number into web browser to capture .png file